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參數(shù)資料
| 型號(hào)： | 28F001BX-T |
| 廠商： | Intel Corp. |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 1兆位（128K的× 8）引導(dǎo)塊閃存 |
| 文件頁數(shù)： | 23/33頁 |
| 文件大小： | 436K |
| 代理商： | 28F001BX-T |
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28F001BX-T/28F001BX-B
AC CHARACTERISTICSDWrite/Erase/Program Operations
(1, 9)
Symbol
Parameter
Notes
28F001BX-70
28F001BX-90
Units
V
CC
e
5V
g
5%
(10)
30 pF
V
CC
e
5V
g
10%
(11)
100 pF
V
CC
e
5V
g
10%
(11)
100 pF
Min
Max
Min
Max
Min
Max
t
AVAV
t
PHWL
t
WC
t
PS
Write Cycle Time
70
75
90
ns
RP
Y
High Recovery to WE
Y
Going Low
2
480
480
480
ns
t
ELWL
t
WLWH
t
PHHWH
t
PHS
RP
Y
V
HH
Setup to WE
Y
Going
High
t
CS
t
WP
CE
Y
Setup to WE
Y
Going Low
10
10
10
ns
WE
Y
Pulse Width
35
40
40
ns
2
100
100
100
ns
t
VPWH
t
AVWH
t
VPS
t
AS
V
PP
Setup to WE
Y
Going High
Address Setup to WE
Y
Going
High
2
100
100
100
ns
3
35
40
40
ns
t
DVWH
t
WHDX
t
WHAX
t
WHEH
t
WHWL
t
WHQV1
t
DS
t
DH
t
AH
t
CH
t
WPH
WE
Y
Pulse Width High
Duration of Programming
Operation
Data Setup to WE
Y
Going High
4
35
40
40
ns
Data Hold from WE
Y
High
10
10
10
ns
Address Hold from WE
Y
High
10
10
10
ns
CE
Y
Hold from WE
Y
High
10
10
10
ns
35
35
35
ns
5, 6, 7
15
15
15
m
s
t
WHQV2
Duration of Erase Operation
(Boot)
5, 6, 7
1.3
1.3
1.3
sec
t
WHQV3
Duration of Erase Operation
(Parameter)
5, 6, 7
1.3
1.3
1.3
sec
t
WHQV4
Duration of Erase Operation
(Main)
5, 6, 7
3.0
3.0
3.0
sec
t
WHGL
t
QVVL
t
QVPH
t
PHBR
Write Recovery before Read
0
0
0
m
s
t
VPH
V
PP
Hold from Valid SRD
t
PHH
RP
Y
V
HH
Hold from Valid SRD
Boot-Block Relock Delay
2, 6
0
0
0
ns
2, 7
0
0
0
ns
2
100
100
100
ns
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A
IN
for byte programming or block erasure.
4. Refer to Table 3 for valid D
IN
for byte programming or block erasure.
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7
e
1). V
PP
should be held at V
PPH
until determination of
program/erase success (SR.3/4/5
e
0).
7. For boot block programming and erasure, RP
Y
should be held at V
HH
until determination of program/erase success
(SR.3/4/5
e
0).
8. Alternate boot block access method.
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See high speed test configuration.
11. See standard test configuration.
23
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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