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| 型號： | 28F001BX-T |
| 廠商： | Intel Corp. |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 1兆位（128K的× 8）引導塊閃存 |
| 文件頁數(shù)： | 29/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | 28F001BX-T |
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28F001BX-T/28F001BX-B
AC CHARACTERISTICS FOR CE
Y
-CONTROLLED WRITES
(1)
Symbol
Parameter
Notes
28F001BX-70
28F001BX-90
Units
V
CC
e
5V
g
5%
(8)
30 pF
V
CC
e
5V
g
10%
(9)
100 pF
V
CC
e
5V
g
10%
(9)
100 pF
Min
Max
Min
Max
Min
Max
t
AVAV
t
WC
Write Cycle Time
70
75
90
ns
t
PHEL
t
PS
RP
Y
High Recovery to CE
Y
Going Low
2
480
480
480
ns
t
WLEL
t
WS
WE
Y
Setup to CE
Y
Going Low
0
0
0
ns
t
ELEH
t
PHHEH
t
PHS
RP
Y
V
HH
Setup to CE
Y
Going
High
t
CP
CE
Y
Pulse Width
50
55
55
ns
2
100
100
100
ns
t
VPEH
t
VPS
V
PP
Setup to CE
Y
Going High
Address Setup to CE
Y
Going
High
2
100
100
100
ns
t
AVEH
t
AS
3
35
40
40
ns
t
DVEH
t
DS
Data Setup to CE
Y
Going High
4
35
40
40
ns
t
EHDX
t
DH
Data Hold from CE
Y
High
10
10
10
ns
t
EHAX
t
AH
Address Hold from CE
Y
High
10
10
10
ns
t
EHWH
t
WH
t
EPH
CE
Y
Pulse Width High
WE
Y
Hold from CE
Y
High
0
0
0
ns
t
EHEL
20
20
20
ns
t
EHQV1
Duration of Programming
Operation
5, 6
15
15
15
m
s
t
EHQV2
Duration of Erase Operation
(Boot)
5, 6
1.3
1.3
1.3
sec
t
EHQV3
Duration of Erase Operation
(Parameter)
5, 6
1.3
1.3
1.3
sec
t
EHQV4
Duration of Erase Operation
(Main)
5, 6
3.0
3.0
3.0
sec
t
EHGL
Write Recovery before Read
0
0
0
m
s
t
QVVL
t
VPH
V
PP
Hold from Valid SRD
t
PHH
RP
Y
V
HH
Hold from Valid SRD
2, 5
0
0
0
ns
t
QVPH
2, 6
0
0
0
ns
t
PHBR
Boot-Block Relock Delay
2
100
100
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE
Y
and WE
Y
. In systems where
CE
Y
defines the write pulse width (within a longer WE
Y
timing waveform), all set-up, hold and inactive WE
Y
times should
be measured relative to the CE
Y
waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A
IN
for byte programming or block erasure.
4. Refer to Table 3 for valid D
IN
for byte programming or block erasure.
5. Program and erase durations are measured to completion (SR.7
e
1). V
PP
should be held at V
PPH
until determination of
program/erase success (SR.3/4/5
e
0).
6. For boot block programming and erasure, RP
Y
should be held at V
HH
until determination of program/erase success
(SR.3/4/5
e
0).
7. Alternate boot block access method.
8. See high speed test configuration.
9. See standard text configuration.
29
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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