- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371434 > 28F001BX-T (Intel Corp.) 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY PDF資料下載
參數(shù)資料
| 型號： | 28F001BX-T |
| 廠商： | Intel Corp. |
| 英文描述： | 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 1兆位（128K的× 8）引導(dǎo)塊閃存 |
| 文件頁數(shù)： | 7/33頁 |
| 文件大?。?/td> | 436K |
| 代理商： | 28F001BX-T |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
28F001BX-T/28F001BX-B
BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Read
The 28F001BX has three read modes. The memory
can be read from any of its blocks, and information
can be read from the Intelligent Identifier or the
Status Register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate read mode
command to the Command Register (array, Intelli-
gent Identifier, or Status Register). The 28F001BX
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The 28F001BX has four control pins, two of which
must be logically active to obtain data at the outputs.
Chip Enable (CE
Y
) is the device selection control,
and when active enables the selected memory de-
vice. Output Enable (OE
Y
) is the data input/output
(DQ
0
–DQ
7
) direction control, and when active
drives data from the selected memory onto the I/O
bus. RP
Y
and WE
Y
must also be at V
IH
. Figure 12
illustrates read bus cycle waveforms.
Output Disable
With OE
Y
at a logic-high level (V
IH
), the device out-
puts are disabled. Output pins (DQ
0
–DQ
7
) are
placed in a high-impedance state.
Standby
CE
Y
at a logic-high level (V
IH
) places the 28F001BX
in standby mode. Standby operation disables much
of the 28F001BX’s circuitry and substantially reduc-
es device power consumption. The outputs (DQ
0
–
DQ
7
) are placed in a high-impedance state indepen-
dent of the status of OE
Y
. If the 28F001BX is dese-
lected during erase or program, the device will
continue functioning and consuming normal active
power until the operation is completed.
Deep Power-Down
The 28F001BX offers a 0.25
m
W V
CC
power-down
feature, entered when RP
Y
is at V
IL
. During read
modes, RP
Y
low deselects the memory, places out-
put drivers in a high-impedance state and turns off
all internal circuits. The 28F001BX requires time
t
PHQV
(see AC Characteristics-Read Only Opera-
tions) after return from power-down until initial mem-
ory access outputs are valid. After this wakeup inter-
val, normal operation is restored. The Command
Register is reset to Read Array, and the Status Reg-
ister is cleared to value 80H, upon return to normal
operation.
During erase or program modes, RP
Y
low will abort
either operation. Memory contents of the block be-
ing altered are no longer valid as the data will be
partially programmed or erased. Time t
PHWL
after
RP
Y
goes to logic-high (V
IH
) is required before an-
other command can be written.
Table 2. 28F001BX Bus Operations
Mode
Notes
RP
Y
CE
Y
OE
Y
WE
Y
A
9
A
0
V
PP
DQ
0–7
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
2
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power Down
2
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
2, 3, 4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
89H
Intelligent Identifier (Device)
2, 3, 4, 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
94H, 95H
Write
2, 6, 7, 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
NOTES:
1. Refer to DC Characteristics. When V
PP
e
V
PPL
, memory contents can be read but not programmed or erased.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PPL
or V
PPH
for V
PP
.
3. See DC Characteristics for V
PPL
, V
PPH
, V
HH
and V
ID
voltages.
4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. A
1
–A
8
,
A
10
–A
16
e
V
IL
.
5. Device ID
e
94H for the 28F001BX-T and 95H for the 28F001BX-B.
6. Command writes involving block erase or byte program are successfully executed only when V
PP
e
V
PPH
.
7. Refer to Table 3 for valid D
IN
during a write operation.
8. Program or erase the boot block by holding RP
Y
at V
HH
or toggling OE
Y
to V
HH
. See AC Waveforms for program/erase
operations.
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F001BX | 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲器) |
| 28F002BC | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BV-B | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F004B3 | 3 Volt Advanced Boot Block Flash Memory(3 V,4M位高級引導(dǎo)塊閃速存儲器) |
| 28F004S3 | BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 28F002BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F002BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。