
28F320D18
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3.3.1
Reading the Protection Register
The protection register is read by using the Read Device Identifier command (90H). Once in this
mode, read cycles from addresses shown in Appendix B retrieve the specified protection register
information. To return to read array mode, use the Read Array command (FFH).
3.3.2
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command.
The 64-bit number is programmed 16 bits at a time. First write the Protection Program Setup
command, C0H. The next write to the device will latch in address and data to program the specified
location. The allowable addresses are shown in Appendix B. See
Figure 12, “Protection Register
Programming Flowchart” on page 30
.
Any attempt to address Protection Program commands outside the defined protection register
address space should not be performed. Attempting to program to a previously locked protection
register segment will result in a status register error (program error bit SR.4 and lock error bit
SR.1 = 1).
3.3.3
Locking the Protection Register
The customer-programmable segment of the protection register is lockable by programming Bit 1
of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to
protect the unique device number. This bit is set using the Protection Program command to
program “FFFD” to the PR-LOCK location. After these bits have been programmed, no further
changes can be made to the values stored in the protection register. Protection Program commands
to a locked section will result in a status register error program error bit SR.4 and lock error bit
SR.1 will be set to 1). Protection register lockout state is not reversible.
Figure 4. Protection Register Memory Map
4 Words
Intel Programmed
4 Words
Customer
Programmed
1 Word Lock
0088H
0085H
0084H
0081H
0080H