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參數(shù)資料
| 型號： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲器） |
| 文件頁數(shù)： | 52/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
48
Product Preview
Different interface considerations need to be made when booting from 1.8 Volt Dual-Plane Flash
memory depending on whether or not the processor supports burst read operations at boot-up.
Case 1, the processor does not support burst read mode at boot-up, but rather boots up in
asynchronous page mode. This is the initial state of the flash memory, so no special design
considerations need to be made. After booting up, the processor can, if possible, configure the
flash memory for synchronous burst mode.
Case 2, the processor does support burst mode at boot-up. After return from reset, the flash
memory defaults to asynchronous read mode, which is inherently slower than synchronous
burst mode. External interface logic will be needed to inform the processor of this, and to
insert wait states to match the flash memory’s timing with the processor’s timing. This logic is
only necessary until the processor has a chance to switch the memory device to synchronous
burst mode, at which time the external logic must be notified of this change. This can be
accomplished via a write-able register within the system wait-state logic or via a general
purpose I/O (GPIO) pin. The GPIO pin may operate as an input into the system logic.
7.3.5
Signal Generation
Other than address and data pins, 1.8 Volt Dual-Plane Flash memory has several control pins as
well. This section will cover these pins and how to generate these signals.
ADV# can be derived from the processor’s transaction start signal. If the processor does not
have this type of signal, other standard CPU control signals can be used to control ADV#. The
key characteristic of this signal is that it must toggle to inform the device to latch a new
address. If this signal is not used, in asynchronous page mode only, then CE# must toggle to
inform the flash memory of a new address.
CLK can be derived from the processor’s memory clock output. If the processor does not
supply this control signal to the memory subsystem, the signal can be received from the clock
signal generator through a clock buffer. This buffer minimizes clock load and skew. The clock
signal must have a period of at least 25 ns.
Figure 20
illustrates different clock options.
Figure 20. Different Clock Options
CPU
Clock
Clock
Buffer
MCLK
INCLK
CLK option 1
CPU provides
a system CLK output
CLK option 2
CPU does not provide
a system CLK output
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