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參數(shù)資料
| 型號： | 28F320D18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲器) |
| 中文描述： | 1.8 V的英特爾雙平面閃存（1.8伏英特爾雙平面閃速存儲器） |
| 文件頁數(shù)： | 25/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | 28F320D18 |
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28F320D18
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21
4.10
Set Read Configuration Command
The Set Read Configuration command writes data to the Read Configuration register (RCR).
This operation is initiated by a two-cycle command sequence. The RCR can be configured by
writing the command at any device address. Read configuration setup is written followed by a
second write that specifies the data to be written to the read configuration register. This data is
placed on the address bus, A
15:0
, and is latched on the rising edge of ADV#, CE#, or WE#
(whichever occurs first). The read configuration data sets the device’s read configuration, burst
order, frequency configuration, and burst length. The command functions independently of the
applied V
PP
voltage. After executing this command, the device returns to read array mode.
Note:
1. The RCR can be read via the Read Device Identification command (90H). Address 00005
contains the RCR data. See
Table 6, “Identifier Codes” on page 16
.
2. All the bits in the RCR are set to “1” on device power-up or reset.
4.10.1
Device Read Configuration
Each partition supports a high performance synchronous burst mode read configuration. A read
configuration register bit sets the read configuration. The RCR can be read via the Read Device
Identification command (90H) at address 00005.
The main partition contains only main blocks and supports asynchronous, page mode, and
synchronous read configurations. Its status register supports only single asynchronous and single
synchronous reads.
The parameter partition’s parameter blocks and status register support only single asynchronous
and single synchronous read operations. Its main blocks support asynchronous, page mode, and
synchronous read configurations.
4.10.2
Frequency Configuration
The frequency configuration informs the device of the number of clocks that must elapse after
ADV# is driven active before data will be available. This value is determined by the input clock
frequency. See
Table 9
for the specific input CLK frequency configuration code.
Figure 5, “Frequency Configuration” on page 22
, illustrates data output latency from ADV# going
active for different frequency configuration codes.
Table 9. Frequency Configuration Settings
Frequency Configuration
Code
Input CLK Frequency
(V
CC
= 1.65 V–1.95 V)
-110 ns
-120 ns
1
Reserved
Reserved
2
≤
24 MHz
≤
21 MHz
3
≤
36 MHz
≤
32 MHz
4
≤
40 MHz
≤
40 MHz
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