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參數(shù)資料
| 型號(hào)： | 49LF002 |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub |
| 中文描述： | 2兆位/ 3兆/ 4兆位/ 8兆固件集線器 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 412K |
| 代理商： | 49LF002 |
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Advance Information
2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
2001 Silicon Storage Technology, Inc.
S71161-06-000
9/01
504
FIGURE 9: CLK WAVEFORM
TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
s
TPU-WRITE1
Power-up to Write Operation
100
s
T12.2 504
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 13: PIN IMPEDANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance
VI/O = 0V
12 pF
CIN1
Input Capacitance
VIN = 0V
12 pF
LPIN2
2. Refer to PCI spec.
Pin Inductance
20 nH
T13.4 504
TABLE 14: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum
Specification
Units
Test Method
NEND1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard 78
T14.3 504
TABLE 15: CLOCK TIMING PARAMETERS
Symbol
Parameter
Min
Max
Units
TCYC
CLK Cycle Time
30
ns
THIGH
CLK High Time
11
ns
TLOW
CLK Low Time
11
ns
-
CLK Slew Rate (peak-to-peak)
1
4
V/ns
-
RST# or INIT# Slew Rate
50
mV/ns
T15.1 504
504 ILL F27.0
0.4 VDD p-to-p
(minimum)
Tcyc
Thigh
Tlow
0.4 VDD
0.3 VDD
0.6 VDD
0.2 VDD
0.5 VDD
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