參數(shù)資料
型號: 56F802
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 18/40頁
文件大?。?/td> 2472K
代理商: 56F802
56F802 Technical Data, Rev. 7
18
Freescale Semiconductor
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in
Table 3-4
)
3.3 AC Electrical Characteristics
Timing waveforms in
Section 3.3
are tested using the V
IL
and V
IH
levels specified in the DC Characteristics
table. In
Figure 3-2
the levels of V
IH
and V
IL
for an input signal are shown.
Figure 3-2 Input Signal Measurement References
9.
drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless
the external power supply drops below the minimum specified value (3.0V).
10. Power
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,
this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally
regulated voltage is typically 100 mV less than V
DD
during ramp up until 2.5V is reached, at which time it self regulates.
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
0
40
80
120
160
10
20
30
40
50
60
70
80
Freq. (MHz)
I
IDD Digital
IDD Analog
IDD Total
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
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