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參數(shù)資料
| 型號： | 56F802 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 2472K |
| 代理商： | 56F802 |
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F802 Technical Data, Rev. 7
Freescale Semiconductor
25
3.5.2
Phase Locked Loop Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-9 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency for the PLL
1
1.
correctly. The PLL is optimized for 8MHz input crystal.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
2.
User Manual. ZCLK = f
op
3.
Will not exceed 60MHz for the DSP56F802TA60 device.
ZCLK may not exceed 80MHz. For additional information on ZCLK and f
out
/2, please refer to the OCCS chapter in the
4.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
f
osc
4
8
10
MHz
PLL output frequency
2
f
out
/2
40
—
80
3
MHz
PLL stabilization time
4
0
o
to +85
o
C
t
plls
—
10
—
ms
PLL stabilization time
4
-40
o
to 0
o
C
t
plls
—
100
200
ms
Table 3-10 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
RESET Assertion to Address, Data and Control Signals High
Impedance
t
RAZ
—
21
ns
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
3.
Parameters listed are guaranteed by design.
t
RA
275,000T
128T
—
—
ns
ns
RESET De-assertion to First External Address Output
t
RDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
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