參數(shù)資料
型號： 72V293L6PFG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 64K X 18 OTHER FIFO, 4 ns, PQFP80
封裝： GREEN, PLASTIC, TQFP-80
文件頁數(shù)： 28/45頁
文件大?。?/td> 381K
代理商： 72V293L6PFG
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
WCLK
tENH
WEN
PAE
RCLK
tENS
n words in FIFO
(2),
n+1 words in FIFO (3)
tPAES
tSKEW2(4)
tPAES
12
REN
4666 drw22
tENS
tENH
n+1 words in FIFO
(2),
n+2 words in FIFO (3)
n words in FIFO
(2),
n+1 words in FIFO(3)
tCLKL
tCLKH
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283
and 131,072 for the IDT72V293.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193
for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073
for the IDT72V293.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
WCLK
tCLKH
tENS
tENH
WEN
PAF
tENS
D
(m + 1)
words in FIFO
RCLK
REN
4666 drw23
D
m words
in FIFO
D
(m + 1) words in FIFO
tCLKL
tPAFA
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
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參數(shù)描述
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72V293L7-5BCI 功能描述:先進先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V293L7-5PF 功能描述:先進先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V293L7-5PF8 功能描述:先進先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V293L7-5PF9 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin TQFP
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