參數(shù)資料
型號(hào): 72V293L6PFG
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): FIFO
英文描述: 64K X 18 OTHER FIFO, 4 ns, PQFP80
封裝: GREEN, PLASTIC, TQFP-80
文件頁(yè)數(shù): 29/45頁(yè)
文件大小: 381K
代理商: 72V293L6PFG
35
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243,
4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths
are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273,
65,536 for the IDT72V283 and 131,072 for the IDT72V293.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097
for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are
selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537
for the IDT72V283 and 131,073 for the IDT72V293.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENS
tENH
WEN
PAE
tENS
n + 1 words in FIFO(2),
n+2wordsinFIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
RCLK
tPAEA
REN
4666 drw24
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
tCLKL
tCLKH
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENS
tENH
WEN
HF
tENS
tHF
RCLK
tHF
REN
4666 drw25
tCLKL
tCLKH
D/2 words in FIFO(1),
[
] words in FIFO(2)
D + 1
2
[ + 1] words in FIFO(1),
[
] + 1 words in FIFO(2)
D + 1
2
D
2
D/2 words in FIFO(1),
[
] words in FIFO(2)
D + 1
2
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