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參數(shù)資料
| 型號： | 72V293L6PFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 64K X 18 OTHER FIFO, 4 ns, PQFP80 |
| 封裝： | GREEN, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 41/45頁 |
| 文件大?。?/td> | 381K |
| 代理商： | 72V293L6PFG |
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IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
to-HIGH transition of WCLK. Similarly, the
PAFisassertedLOWontheLOW-
to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF configuration is selected , the PAE is asserted
and updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. The
modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the
RT input during a rising RCLK edge initiates a
retransmitoperationbysettingthereadpointertothefirstlocationofthememory
array. A zero-latency retransmit timing mode can be selected using the
RetransmittimingModepin(RM).DuringMasterReset,aLOWonRMwillselect
zero-latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmitted will be placed on the output register with respect to the same
RCLK edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
IW
OW
Write Port Width
Read Port Width
L
x18
L
H
x18
x9
H
L
x9
x18
H
x9
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (
BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFOwillassumethattheparitybitislocatedinbitpositionD8 duringtheparallel
programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then
D8isassumedtobeavalidbitandD16 andD17 areignored.IPmodeisselected
during Master Reset by the state of the IP input pin. This mode is relevant only
when the input width is set to x18 mode. Interspersed Parity control only has
aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe
data written to and read from the FIFO.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are fabricated using IDT’s high speed submicron CMOS technology.
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| 7305-0-15-01-47-01-10-0 | BERYLLIUM COPPER, TIN LEAD (300) OVER NICKEL FINISH, PCB TERMINAL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72V293L7-5BC | 功能描述:先進(jìn)先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V293L7-5BCI | 功能描述:先進(jìn)先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V293L7-5PF | 功能描述:先進(jìn)先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V293L7-5PF8 | 功能描述:先進(jìn)先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V293L7-5PF9 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin TQFP |
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