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| 型號(hào)： | 73S1210F-EB-LITE |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 46/126頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 73S1210F LITE DOC/CBL |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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73S1210F Data Sheet
DS_1210F_001
26
Rev. 1.4
VBAT is expected to be supplied from a battery of three to four series connected cells with a voltage value
of 4.0 to 6.5 volts.
VBAT and VBUS are internally switched to VPC by two separate FET switches configured as a SPDT switch
(break-before-make). They will not be enabled at the same time. VBUS is automatically selected in lieu of
VBAT when VBUS is present (i.e. VBUS always has the priority).
If VPC is provided and either VBAT or VBUS is also used, the source of VPC must be diode isolated from the
VPC pin to prevent current flow from VBAT or VBUS into the VPC source.
The power that is supplied to the VPC pin (externally or internally, i.e. through VBAT or VBUS – see above) is
up-converted to the intermediate voltage VP utilizing an inductive, step-up converter. A series power
inductor (nominal value = 10
H) must be connected from V
PC to the pin LIN, and a 10F low ESR filter
capacitor must be connected to VPC.
VP requires a 4.7F filter capacitor and will have a nominal value of 5.5 volts during normal operation. VP
is used internally by the smart card electrical interface circuit and is regulated to the desired smart card
supply VCC voltage (can be programmed for values of 5V, 3V, or 1.8V).
VP is also used internally to generate a 3.3V nominal, regulated power supply VDD. VDD is output on pin
68 and must be directly tied to all other VDD pins on the 73S1210F (pins 28 and 40). VDD powers all the
digital logic, input/output buffering, and analog functions. It can also be used for external circuitry: up to
20mA current can be supplied to external devices simultaneously to the 73S1210F’s digital core
maximum consumption.
1.7.3
Power ON/OFF
The 73S1210F features an ON_OFF input pin for a momentary contact, main-system ON/OFF switch. The
purpose of this switch is to place the circuit in a very low-power mode – the “OFF” mode – where all circuits
are no longer powered, therefore allowing the lowest possible current consumption.
When in “OFF” mode, an action on the ON/OFF switch will turn-on the power supply of the digital core
(VDD) and apply a power-on-reset condition. Alternatively, entering the “OFF” mode from the “ON” mode
requires firmware action.
When in “ON” mode, an action on the ON/OFF switch will send a request to the controller that will have to
be acknowledged (firmware action required) in order to enter the “OFF” state.
When placed into the “OFF” state, the 73S1210F will consume minimum current from VPC and VBAT; VP
and VDD will be unavailable (VDD out = 0V and VP = 0V).
When in “ON” mode, the 73S1210F will operate normally, with all the features described in this document
available. VP and VDD will be available (VDD out = 3.3V and VP = 5.5V nominal).
Whenever VBUS power is supplied, the circuit will be automatically in the “ON” state. The functions of the
ON/OFF switch and circuitry are overridden and the 73S1210F is in the “ON” state with VP and VDD available.
Without VBUS applied, the circuit is by default in the “OFF” state, and will respond only to the ON_OFF pin.
The ON_OFF pin should be connected to an SPST switch to ground. If the circuit is OFF and the switch
is closed for a debounce period of 50-100ms, the circuit will go into the “ON” state wherein all functions
are operating in normal fashion. If the circuit is in the “ON” state and the ON/OFF pin is connected to
ground for a period greater than the debounce period, OFF_REQ will be asserted high and held
regardless of the state of ON/OFF. The OFF_REQ signal should be connected to one of the interrupt
pins to signal the CPU core that a request to shutdown has been initiated. The firmware will
acknowledge this request by setting the SCPWRDN bit in the Smart Card VCC Control/Status Register
(VccCtl) high after it has completed all shutdown activities. When SCPWRDN is set high, the circuit will
deactivate the smart card interface if required and turn off all analog functions and the VDD supply for the
logic and companion circuits. The default state upon application of power is the “OFF” state unless
power is supplied to the VBUS supply. Note that at any time, the firmware may assert SCPWRDN and the
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