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型號(hào)：	79RC32V333-150DH
英文描述：	8 PIN, 1.75KB, FLASH, 64B RAM, COMPARATOR, 8MHZ INTERNAL OSCILLATOR, -40C to +125C, 8-PDIP, TUBE
中文描述：	微處理器
文件頁(yè)數(shù)：	554/654頁(yè)
文件大?。?/td>	6963K
代理商：	79RC32V333-150DH

Understanding the Instruction Set

79RC32355 User Reference Manual

November 4, 2002

Figure A.5 Example of Instruction Description

The body of the section is a description of the operation of the instruction in text, tables, and figures.

This description complements the high-level language description in the Operation section.

This section uses acronyms for register descriptions. “GPR rt” is CPU general-purpose register specified

by the instruction field rt.

Restrictions Field

The Restrictions field documents any possible restrictions that may affect the instruction. Most restric-

tions fall into one of the following six categories:

Valid values for instruction fields (for example, see floating-point ADD.fmt)

Alignment requirements for memory addresses (for example, see LW)

Valid values of operands (for example, see DADD)

Valid operand formats (for example, see floating-point ADD.fmt)

Order of instructions necessary to guarantee correct execution. These ordering constraints avoid

pipeline hazards for which some processors do not have hardware interlocks (for example, see

Valid memory access types (for example, see LL/SC).

Figure A.6 Example of Instruction Restrictions

Operation Field

The Operation field describes the operation of the instruction as pseudocode in a high-level language

notation resembling Pascal (see Figure A.7). This formal description complements the Description section;

it is not complete in itself because many of the restrictions are either difficult to include in the pseudocode or

are omitted for legibility.

Description: rd rs + rt

The 32-bit word value in GPR rt is added to the 32-bit value in DPR rs to produce a 32-bit result.

If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not

modified and an Integer Overflow exception occurs.

If the addition does not overflow, the 32-bit result is placed into GPR rd.

Restrictions:

Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT

instruction is placed in the delay slot of a branch or jump.

相關(guān)PDF資料	PDF描述
79RC32V333-150DHI	Microprocessor
79RC32V334-100BB	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-100BBI	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-133BB	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-133BBI	MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
79RC32V333-150DHI	制造商:未知廠家制造商全稱:未知廠家功能描述:Microprocessor
79RC32V334-100BB	制造商:未知廠家制造商全稱:未知廠家功能描述:MICROPROCESSOR\|32-BIT\|BGA\|256PIN\|PLASTIC
79RC32V334-100BBG	制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 32-Bit 100MHz 3.3V 256-Pin BGA
79RC32V334-100BBGI	制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 32-Bit 100MHz 3.3V 256-Pin BGA
79RC32V334-100BBI	制造商:Integrated Device Technology Inc 功能描述:MPU RC32300 32-Bit 100MHz 3.3V 256-Pin BGA

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