參數(shù)資料
型號(hào)： 80960JS
廠商： Intel Corp.
英文描述： High Performance 32-bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式微處理器3.3（3.3高性能32位嵌入式處理器）
文件頁(yè)數(shù)： 10/86頁(yè)
文件大?。?/td> 1257K
代理商： 80960JS
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
10
Datasheet
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core
’
s performance include:
Core operates at the bus speed with the 80960JA/JF/JS
Core operates at two or three times the bus speed with the 80960JD/JC and 80960JT,
respectively
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
Two-way set associative, integrated instruction cache
Direct-mapped, integrated data cache
1-Kbyte integrated data RAM delivers zero wait state program data
2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx
’
s bus controller to match an application
’
s fundamental memory
organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and
data caching are programmed through a group of logical memory templates and a defaults register.
The BCU
’
s features include:
Multiplexed external bus to minimize pin count
32-, 16-, and 8-bit bus widths to simplify I/O interfaces
External ready control for address-to-data, data-to-data and data-to-next-address wait state types
Support for big or little endian byte ordering to facilitate the porting of existing program code
Unaligned bus accesses performed transparently
Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
相關(guān)PDF資料
PDF描述
80960JC High Performance 32-Bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
80960KB Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點(diǎn)單元的嵌入式32位微處理器)
80960MC Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點(diǎn)單元和存儲(chǔ)器管理單元的嵌入式32位微處理器)
80960RM 80960RM I/O Processor(80960RM I/O 處理器)
80960RN 80960RN I/O Processor(80960RN I/O 處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80960JT 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR
80960KA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960KB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT
80960MC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
80960SA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*