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80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
4
Datasheet
Figures
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11
80960Jx Microprocessor Package Options...........................................................7
80960Jx Block Diagram ........................................................................................9
132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23
132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................24
132-Lead PQFP - Top View................................................................................27
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down .................30
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up .................31
VCC5 Current-Limiting Resistor..........................................................................42
VCCPLL Lowpass Filter......................................................................................43
AC Test Load ......................................................................................................51
Output Delay or Hold vs. Load Capacitance
–
80960JS/JC/JT
(3.3 V Signals) ....................................................................................................51
Output Delay or Hold vs. Load Capacitance
–
80960JS/JC/JT
(5 V Signals) .......................................................................................................52
Output Delay or Hold vs. Load Capacitance
–
80960JA/JF/JD ..........................52
T
LX
vs. AD Bus Load Capacitance
–
80960JS/JC/JT (3.3 V Signals) ................53
T
LX
vs. AD Bus Load Capacitance
–
80960JS/JC/JT (5 V Signals) ...................53
T
LX
vs. AD Bus Load Capacitance
–
80960JA/JF/JD.........................................54
I
CC
Active (Power Supply) vs. Frequency
–
80960JA/JF....................................55
80960JA/JF I
CC
Active (Thermal) vs. Frequency................................................55
80960JD I
CC
Active (Power Supply) vs. Frequency............................................56
80960JD I
CC
Active (Thermal) vs. Frequency.....................................................56
80960JC I
CC
Active (Power Supply) vs. Frequency............................................57
80960JC I
CC
Active (Thermal) vs. Frequency.....................................................57
80960JS I
CC
Active (Power Supply) vs. Frequency............................................58
80960JS I
CC
Active (Thermal) vs. Frequency.....................................................58
CLKIN Waveform ................................................................................................59
T
OV1
Output Delay Waveform.............................................................................59
T
OF
Output Float Waveform................................................................................60
T
IS1
and T
IH1
Input Setup and Hold Waveform...................................................60
T
IS2
and T
IH2
Input Setup and Hold Waveform...................................................60
T
IS3
and T
IH3
Input Setup and Hold Waveform...................................................61
T
IS4
and T
IH4
Input Setup and Hold Waveform...................................................61
T
LX
, T
LXL
and T
LXA
Relative Timings Waveform.................................................62
DT/R# and DEN# Timings Waveform .................................................................62
TCK Waveform....................................................................................................63
T
BSIS1
and T
BSIH1
Input Setup and Hold Waveforms .........................................63
T
BSOV1
and T
BSOF1
Output Delay and Output Float Waveform..........................63
T
BSOV2
and T
BSOF2
Output Delay and Output Float Waveform..........................64
T
BSIS2
and T
BSIH2
Input Setup and Hold Waveform...........................................64
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........65
Burst Read and Write Transactions Without Wait States, 32-Bit Bus.................66
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................67
Burst Read and Write Transactions Without Wait States, 8-Bit Bus...................68
Burst Read and Write Transactions With 1, 0 Wait States and
Extra Tr State on Read, 16-Bit Bus.....................................................................69
Double Word Read Bus Request, Misaligned One Byte From
Quad Word Boundary, 32-Bit Bus, Little Endian.................................................70
HOLD/HOLDA Waveform For Bus Arbitration ....................................................71
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