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參數(shù)資料
| 型號(hào)： | 82845GV |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA760 |
| 封裝： | 37.50 X 37.50 MM, 1 MM PITCH, FLIP CHIP, BGA-760 |
| 文件頁(yè)數(shù)： | 81/193頁(yè) |
| 文件大?。?/td> | 2990K |
| 代理商： | 82845GV |
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Intel
82845G/82845GL/82845GV GMCH Datasheet
81
Register Description
3.5.2.4
PCISTS1—PCI Status Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
06–07h
00A0h
RO, R/WC
16 bits
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the “virtual” PCI-to-PCI bridge embedded within the GMCH.
Bit
Description
15
Detected Parity Error (DPE)—RO.
Hardwired to 0. Parity is not supported on the primary side of
this device.
14
Signaled System Error (SSE)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set to 1 when GMCH Device 1 generates an SERR message over the hub interface
for any enabled Device 1 error condition. Device 1 error conditions are enabled in the
ERRCMD, PCICMD1 and BCTRL1 registers. Device 1 error flags are read/reset from the
ERRSTS and SSTS1 register.
13
Received Master Abort Status (RMAS)—RO.
Hardwired to 0. The concept of a master abort does
not exist on primary side of this device.
12
Received Target Abort Status (RTAS)—RO.
Hardwired to 0. The concept of a target abort does
not exist on primary side of this device. T
11
Signaled Target Abort Status (STAS)—RO.
Hardwired to 0. The concept of a target abort does not
exist on primary side of this device.
10:9
DEVSEL# Timing (DEVT)—RO.
Hardwired to 00. The GMCH does not support subtractive
decoding devices on bus 0. This bit field is therefore hardwired to 00 to indicate that Device 1 uses
the fastest possible decode.
8
Data Parity Detected (DPD)—RO.
Hardwired to 0. Parity is not supported on the primary side of
this device.
7
Fast Back-to-Back (FB2B)—RO.
Hardwired to 1. This indicates that the AGP/PCI_B interface
always supports fast back to back writes.
6
Reserved.
5
66/60MHz Capability (CAP66)—RO.
Hardwired to 1. The AGP/PCI bus is 66 MHz capable.
4:0
Reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82845Gx | Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845Mx | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845GX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
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