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參數(shù)資料
| 型號(hào)： | 8427DY-02LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 500 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 1597K |
| 代理商： | 8427DY-02LFT |
IDT / ICS LVHSTL FREQUENCY SYNTHESIZER
2
ICS8427DY-02 REV A OCTOBER 13, 2006
ICS8427-02
500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
NOTE: The functional description that follows describes op-
eration using a 16.6667MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined in
the Input Frequency Characteristics, Table 6 NOTE 1.
The ICS8427-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. With a 16.6667MHz crystal, this pro-
vides a 1.0417MHz reference frequency. The VCO of the PLL
operates over a range of 250MHz to 500MHz. The output of the
M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The ICS8427-02 powers up by default to 200MHz output fre-
quency, using a 16.6667MHz crystal (M = 192, N = 2). The
output frequency can be changed after power-up by using the
serial interface to program the M feedback divider and the N
output divider.
The relationship between the VCO frequency, the crystal fre-
quency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16.6667MHz
reference are defined as 120
≤ M ≤ 240. The frequency out is
defined as follows:
Serial operation occurs when S_LOAD is LOW. The shift
register is loaded by sampling the S_DATA bits with the rising
edge of S_CLOCK. The contents of the shift register are loaded
into the M divider and N output divider when S_LOAD transi-
tions from LOW-to-HIGH. The M divide and N output
divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N outputdivider on each
rising edge of S_CLOCK. The serial mode can be used to pro-
gram the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output
as follows:
FUNCTIONAL DESCRIPTION
N
fout = fVCO =
16
2M
fxtal x
N
16
fVCO =
fxtal x 2M
T1
T0
TEST Output
00
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. SERIAL LOAD OPERATIONS
t
S
t
H
t
S
Time
S_CLOCK
S_DATA
S_LOAD
NOTE: Default Output Frequency, using a 16.6667MHz crystal
on power-up = 200MHz (M = 192, N = 2) SSC off
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
SSC
(Power-up
Default)
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