參數(shù)資料
型號(hào)： 8427DY-02LFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： XO, clock
英文描述： 500 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
文件頁(yè)數(shù)： 4/23頁(yè)
文件大?。?/td> 1597K
代理商： 8427DY-02LFT
IDT / ICS LVHSTL FREQUENCY SYNTHESIZER
12
ICS8427DY-02 REV A OCTOBER 13, 2006
ICS8427-02
500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied
from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8427-02 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 3 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 3. POWER SUPPLY FILTERING
10
V
DDA
10
F
.01
F
2.5V
.01
F
V
DD
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