參數(shù)資料
型號(hào)： 8427DY-02LFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： XO, clock
英文描述： 500 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
文件頁(yè)數(shù)： 5/23頁(yè)
文件大?。?/td> 1597K
代理商： 8427DY-02LFT
IDT / ICS LVHSTL FREQUENCY SYNTHESIZER
13
ICS8427DY-02 REV A OCTOBER 13, 2006
ICS8427-02
500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8427-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 4 below were determined using a 16.66MHz, 18pF parallel
Figure 4. CRYSTAL INPUt INTERFACE
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 5. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
FIGURE 5. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
applications, R1
and R2 can be 100
. This can also be accomplished by removing
R1 and making R2 50
.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
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