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參數(shù)資料
| 型號： | 935230920112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大小： | 234K |
| 代理商： | 935230920112 |
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2000 Jan 04
30
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. When the transmit error counter exceeds the limit of 255, the bus status bit is set to logic 1 (bus-off), the
CAN controller will set the reset mode bit to logic 1 (present) and an error warning interrupt is generated, if enabled.
The transmit error counter is set to 127 and the receive error counter is cleared. It will stay in this mode until the CPU
clears the reset mode bit. Once this is completed the CAN controller will wait the minimum protocol-defined time
(128 occurrences of the bus-free signal) counting down the transmit error counter. After that the bus status bit is
cleared (bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error warning interrupt
is generated, if enabled. Reading the TX error counter during this time gives information about the status of the
bus-off recovery.
2. Errors detected during reception or transmission will effect the error counters according to the CAN 2.0B protocol
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit (EWLR). An error warning interrupt is generated, if enabled. The default value of EWLR after hardware
reset is 96.
3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle. If both bits are set the
controller is waiting to become idle again. After a hardware reset 11 consecutive recessive bits have to be detected
until the idle status is reached. After bus-off this will take 128 of 11 consecutive recessive bits.
4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit or the self
reception request bit is set to logic 1. The transmission complete status bit will remain at logic 0 until a message is
transmitted successfully.
5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is logic 0 (locked), the written byte
will not be accepted and will be lost without this being indicated.
6. When a message that is to be received has passed the acceptance filter successfully, the CAN controller needs
space in the RXFIFO to store the message descriptor and for each data byte which has been received. If there is not
enough space to store the message, that message is dropped and the data overrun condition is indicated to the CPU
at the moment this message becomes valid. If this message is not completed successfully (e.g. due to an error), no
overrun condition is indicated.
7. After reading all messages within the RXFIFO and releasing their memory space with the command release receive
buffer this bit is cleared.
SR.1
DOS
Data Overrun Status;
note 6
1
overrun; a message was lost because there was
not enough space for that message in the RXFIFO
0
absent; no data overrun has occurred since the
last clear data overrun command was given
SR.0
RBS
Receive Buffer Status;
note 7
1
full; one or more complete messages are available
in the RXFIFO
0
empty; no message is available
BIT
SYMBOL
NAME
VALUE
FUNCTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935246150005 | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC |
| 935230900112 | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 06NU06NU | INNENGEWINDE BSP DREHB G 0.38 |
| 08NU06NU | INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL |
| 08NU08NU | INNENGEWINDE BSP DREHB G 0.5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 935241-1 | 制造商:DIGITRAN 功能描述: 制造商:DTRAN 功能描述: |
| 935245650125 | 制造商:NXP Semiconductors 功能描述:Inverter 1-Element CMOS 5-Pin TSSOP T/R |
| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
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