參數(shù)資料
型號： 935230920112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： 7.50 MM, PLASTIC, SO-28
文件頁數(shù)： 9/68頁
文件大?。?/td> 234K
代理商： 935230920112
2000 Jan 04
17
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.3.6
INTERRUPT REGISTER (IR)
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, the
INT pin is activated (LOW). After this register is read by the microcontroller, all bits are reset what results in a floating
level at INT. The interrupt register appears to the microcontroller as a read only memory.
Table 6
Bit interpretation of the interrupt register (IR); CAN address 3
Notes
1. Reading this bit will always reflect a logic 1.
2. A wake-up interrupt is also generated if the CPU tries to set go to sleep while the CAN controller is involved in bus
activities or a CAN interrupt is pending.
3. The overrun interrupt bit (if enabled) and the data overrun status bit are set at the same time.
4. The receive interrupt bit (if enabled) and the receive buffer status bit are set at the same time.
It should be noted that the receive interrupt bit is cleared upon a read access, even if there is another message
available within the FIFO. The moment the release receive buffer command is given and there is another message
valid within the receive buffer, the receive interrupt is set again (if enabled) with the next tscl.
BIT
SYMBOL
NAME
VALUE
FUNCTION
IR.7
reserved; note 1
IR.6
reserved; note 1
IR.5
reserved; note 1
IR.4
WUI
Wake-Up Interrupt;
note 2
1
set; this bit is set when the sleep mode is left
0
reset; this bit is cleared by any read access of the
microcontroller
IR.3
DOI
Data Overrun Interrupt;
note 3
1
set; this bit is set on a ‘0-to-1’ transition of the data
overrun status bit, when the data overrun interrupt
enable is set to logic 1 (enabled)
0
reset; this bit is cleared by any read access of the
microcontroller
IR.2
EI
Error Interrupt
1
set; this bit is set on a change of either the error
status or bus status bits if the error interrupt
enable is set to logic 1 (enabled)
0
reset; this bit is cleared by any read access of the
microcontroller
IR.1
TI
Transmit Interrupt
1
set; this bit is set whenever the transmit buffer
status changes from logic 0 to logic 1 (released)
and transmit interrupt enable is set to logic 1
(enabled)
0
reset; this bit is cleared by any read access of the
microcontroller
IR.0
RI
Receive Interrupt; note 4
1
set; this bit is set while the receive FIFO is not
empty and the receive interrupt enable bit is set
to logic 1 (enabled)
0
reset; this bit is cleared by any read access of the
microcontroller
相關(guān)PDF資料
PDF描述
935246150005 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
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