參數(shù)資料
型號： 935230920112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： 7.50 MM, PLASTIC, SO-28
文件頁數(shù)： 26/68頁
文件大小： 234K
代理商： 935230920112
2000 Jan 04
32
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. A wake-up interrupt is also generated, if the CPU tries to set the sleep bit while the CAN controller is involved in bus
activities or a CAN interrupt is pending.
2. The behaviour of this bit is equivalent to that of the receive buffer status bit with the exception, that RI depends on
the corresponding interrupt enable bit (RIE). So the receive interrupt bit is not cleared upon a read access to the
interrupt register. Giving the command ‘release receive buffer’ will clear RI temporarily. If there is another message
available within the FIFO after the release command, RI is set again. Otherwise RI remains cleared.
6.4.7
INTERRUPT ENABLE REGISTER (IER)
The register allows to enable different types of interrupt sources which are indicated to the CPU.
The interrupt enable register appears to the CPU as a read/write memory.
Table 16 Bit interpretation of the interrupt enable register (IER); CAN address 4
BIT
SYMBOL
NAME
VALUE
FUNCTION
IER.7
BEIE
Bus Error Interrupt
Enable
1
enabled; if an bus error has been detected, the
CAN controller requests the respective interrupt
0
disabled
IER.6
ALIE
Arbitration Lost Interrupt
Enable
1
enabled; if the CAN controller has lost arbitration,
the respective interrupt is requested
0
disabled
IER.5
EPIE
Error Passive Interrupt
Enable
1
enabled; if the error status of the CAN controller
changes from error active to error passive or vice
versa, the respective interrupt is requested
0
disabled
IER.4
WUIE
Wake-Up Interrupt
Enable
1
enabled; if the sleeping CAN controller wakes up,
the respective interrupt is requested
0
disabled
IER.3
DOIE
Data Overrun Interrupt
Enable
1
enabled; if the data overrun status bit is set (see
status register; Table 14), the CAN controller
requests the respective interrupt
0
disabled
IER.2
EIE
Error Warning Interrupt
Enable
1
enabled; if the error or bus status change (see
status register; Table 14), the CAN controller
requests the respective interrupt
0
disabled
IER.1
TIE
Transmit Interrupt Enable
1
enabled; when a message has been successfully
transmitted or the transmit buffer is accessible
again (e.g. after an abort transmission command),
the CAN controller requests the respective
interrupt
0
disabled
IER.0
RIE
Receive Interrupt
Enable; note 1
1
enabled; when the receive buffer status is ‘full’ the
CAN controller requests the respective interrupt
0
disabled
相關PDF資料
PDF描述
935246150005 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
相關代理商/技術參數(shù)
參數(shù)描述
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935241-1 制造商:DIGITRAN 功能描述: 制造商:DTRAN 功能描述:
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