參數(shù)資料
型號(hào): 935230920112
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝: 7.50 MM, PLASTIC, SO-28
文件頁數(shù): 55/68頁
文件大小: 234K
代理商: 935230920112
2000 Jan 04
59
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
10 AC CHARACTERISTICS
VDD =5V ±10%; VSS =0V; CL = 50 pF (output pins); Tamb = 40 to +125 °C; unless otherwise specied; note 1.
Notes
1. AC characteristics are not tested during production.
2. The analog input comparator may be bypassed internally using the CBP bit in the clock divider register, if external
transceiver circuitry is used. This results in reduced delays (<26 ns). VI(RX) = input voltage on pins RX0 and RX1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
fosc
oscillator frequency
24
MHz
tsu(A-AL)
address set-up to ALE/AS LOW
8
ns
th(AL-A)
address hold after ALE LOW
2
ns
tW(AL)
ALE/AS pulse width
8
ns
tRLQV
RD LOW to valid data output
Intel mode
50
ns
tEHQV
E HIGH to valid data output
Motorola mode
50
ns
tRHDZ
data oat after RD HIGH
Intel mode
30
ns
tELDZ
data oat after E LOW
Motorola mode
30
ns
tDVWH
input data valid to WR HIGH
Intel mode
8
ns
tWHDX
input data hold after WR HIGH
Intel mode
8
ns
tWHLH
WR HIGH to next ALE HIGH
15
ns
tELAH
E LOW to next AS HIGH
Motorola mode
15
ns
tsu(i)(D-EL)
input data set-up to E LOW
Motorola mode
8
ns
th(i)(EL-D)
input data hold after E LOW
Motorola mode
8
ns
tLLWL
ALE LOW to WR LOW
Intel mode
10
ns
tLLRL
ALE LOW to RD LOW
Intel mode
10
ns
tLLEH
AS LOW to E HIGH
Motorola mode
10
ns
tsu(R-EH)
set-up time of RD/WR to E
HIGH
Motorola mode
5
ns
tW(W)
WR pulse width
Intel mode
20
ns
tW(R)
RD pulse width
Intel mode
40
ns
tW(E)
E pulse width
Motorola mode
40
ns
tCLWL
CS LOW to WR LOW
Intel mode
0
ns
tCLRL
CS LOW to RD LOW
Intel mode
0
ns
tCLEH
CS LOW to E HIGH
Motorola mode
0
ns
tWHCH
WR HIGH to CS HIGH
Intel mode
0
ns
tRHCH
RD HIGH to CS HIGH
Intel mode
0
ns
tELCH
E LOW to CS HIGH
Motorola mode
0
ns
tW(RST)
RST pulse width
100
ns
Input comparator/output driver
tSD
sum of input and output delays
VDD =5V ±10%;
VDIF = ±32 mV;
1.4V<VI(RX) <VDD 1.4 V;
note 2
40
ns
相關(guān)PDF資料
PDF描述
935246150005 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
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