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參數(shù)資料
| 型號： | 9860 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級10/100中繼器與綜合管理 |
| 文件頁數(shù)： | 101/118頁 |
| 文件大?。?/td> | 1648K |
| 代理商： | 9860 |
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Advanced 10/100 Repeater with Integrated Management
—
LXT9860/9880
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
101
6.4
Repeater Port Control Registers
The Control Register set includes general port control as well as link and learn enable registers.
6.4.1
General Port Control Registers
The General Port Control Register bit assignments are described in
Table 55
. Refer to
Table 56
for
the General Port Control Register descriptions.
6.4.2
Port Link Control Register
The Port Link Control Register bit assignments are described in
Table 57
. Refer to
Table 58
for the
Port Link Control Register description.
Table 55. Port Control Register Bit Assignments
31:10
9
8
7
6
5
4
3
2
1
0
Rsvd
Port 10
(MII 2)
Port 9
(MII 1)
Port 8
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
1. Bits 8 and 9 (MII Ports) are not used by the Link Control Register.
Table 56. General Port Control Registers
Name
Type
1
Addr
Description
Default
Port Alternate Partition
Algorithm Control
(100 Mbps Only)
R/W
108
Un-partition. The LXT98x0 twisted-pair ports support two
un-partition algorithms:
The alternative un-partition algorithm, which complies with
IEEE specification 802.3aa, un-partitions a port on
either
transmit or receive of at least 450-560 bits without
collision.
The normal algorithm, which complies with the IEEE
specification 802.3u, is available through the management
interface. This algorithm un-partitions a port only when
data is transmitted to the port for 450-560 bit times without
a collision.
Provides per-port selection of partition algorithms.
0 = normal
1 = alternate
1
Port Enable
R/W
109
This register controls whether a port is enabled/disabled.
If the MGR_PRES signal is Low on power up, then all
ports are disabled until such time that management
software re-enables them. Otherwise, the ports are
enabled at power-up.
0 = disable
1 = enable
1
1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. Alternate partition mode also causes port to partition after a single long collision.
Table 57. Port Link Control and Status Register Bit Assignments
31:8
7
6
5
4
3
2
1
0
Rsvd
Port 8
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
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