
LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
94
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
PHY Port Control
Auto Negotiate Advertise (ports 1)
16
R/W
12A
107
Auto Negotiate Advertise (ports 2)
16
R/W
12B
107
Auto Negotiate Advertise (ports 3)
16
R/W
12C
107
Auto Negotiate Advertise (ports 4)
16
R/W
12D
107
Auto Negotiate Advertise (ports 5)
16
R/W
12E
107
Auto Negotiate Advertise (ports 6)
16
R/W
12F
107
Auto Negotiate Advertise (ports 7)
16
R/W
130
107
Auto Negotiate Advertise (ports 8)
16
R/W
131
107
PHY Port Control Register (port 1)
16
R/W
132
107
PHY Port Control Register (port 2)
16
R/W
133
107
PHY Port Control Register (port 3)
16
R/W
134
107
PHY Port Control Register (port 4)
16
R/W
135
107
PHY Port Control Register (port 5)
16
R/W
136
107
PHY Port Control Register (port 6)
16
R/W
137
107
PHY Port Control Register (port 7)
16
R/W
138
107
PHY Port Control Register (port 8)
16
R/W
139
107
Repeater Port
Control/
Status
Repeater Configuration
32
R/W
13A
108
Repeater Serial Configuration
8
R
13B
108
Device/Rev ID
32
R
13C
108
Reserved
32
R
13D
108
Reserved
32
R
13E
108
Reserved
32
R
13F
108
Global LED Control Register
6
R/W
140
108
Port LED Control Register
20
R/W
141
108
LED Timer Control Register
16
R/W
142
108
MII Status
2
R
143
103
Repeater Reset
1
W
144
108
Software Reset
1
W
145
109
Interrupt Status
16
R(/W)
2
146
113
Interrupt Mask
16
R/W
147
113
Serial
Controller
Assign Address
32
W
188, 189
108
PROM Address
32
R
190, 191
108
Table 45. Register Map (Continued)
Class
Register
Size
(Bits)
Access
1
Offset
(Hex)
Page
Ref.
1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing.
2. If Register Clear bit is set to
‘
1
’
, then clearing of the associated bit is done by writing
‘
1
’
to it, otherwise this
register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.
(Refer to
Table 75 on page 109
.)