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參數(shù)資料
| 型號(hào)： | 9860 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級(jí)10/100中繼器與綜合管理 |
| 文件頁數(shù)： | 108/118頁 |
| 文件大?。?/td> | 1648K |
| 代理商： | 9860 |
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LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
108
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
6.8
Repeater Port Control/Status Registers
The Configuration Register set is described in
Table 74
. Configuration Register definitions and bit
assignments are shown in
Table 73
through
Table 76
.
Table 73. PHY Port Control Bit Definitions
Bit
Name
Description
Type
1
Default
31:16
Reserved
Reserved
R
0
15
Reserved
Write as 0; ignore on read.
R/W
0
14
Loopback
Value is
“
O
”
only.
R
0
13
Speed Selection
1 = 100 Mbps.
0 = 10 Mbps.
R/W
0
12
Auto-Negotiation Enable
1 = Enable Auto-Negotiation Process.
0 = Disable Auto-Negotiation Process.
R/W
1
11
Reserved
Write as 0; ignore on read.
R/W
0
10
Reserved
Write as 0; ignore on read.
R/W
0
9
Restart
Auto-Negotiation
1 = Restart Auto-Negotiation Process.
0 = Normal operation.
R/W
SC
0
8
Duplex Mode
1 = Full-Duplex.
0 = Half-Duplex.
R
0
7
Collision Test
1 = Enable COL signal test.
0 = Disable COL signal test.
R/W
0
6:0
Reserved
Write as 0, ignore on Read.
R/W
0000000
1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing
Table 74. Configuration Registers
Name
Type
1
Addr
Description
Repeater Configuration Register
R/W
13A
Refer to
Table 75
for bit assignments.
Repeater Serial Configuration
Register
R
13B
This register holds user-defined data. These bits may
be used to indicate the type of board configuration, port
count or other vendor-related data. Default is set by
pins. Refer to
Table 76
for bit assignments.
Device/Revision ID register
R
13C
This register follows the IEEE 1149.1 specification.
Refer to
Table 77
for bit assignments.
The upper 4 bits identify the device revision level. The
next 16 bits store the Part ID Number. The next 11 bits
contain a JEDEC Manufacturer ID, which for Intel is
hexadecimal
‘
FE
’
. The lowest bit (0) is set only for the
first device in a chain. The encoding scheme used for
the Product ID field is implementation dependent.
Reserved
R
13D
-
Reserved
R
13E
-
Reserved
R
13F
-
1. R = Read only; W = Write only; R/W = Read /Write.
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