參數(shù)資料
型號: 9LRS4103BKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MLF-32
文件頁數(shù): 11/15頁
文件大?。?/td> 188K
代理商: 9LRS4103BKLFT
IDT PC MAIN CLOCK
1520D—01/06/11
ICS9LRS4103
PC MAIN CLOCK
5
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Clk Stabilization
TSTAB
From VDD Power-Up or de-assertion of
PD# to 1st clock
11.8
ms
1
Tfall_PD#
TFALL
5ns
1
Trise_PD#
TRISE
5ns
1
Fall/rise time of PD#, PCI_STOP# and
CPU_STOP# inputs
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
2.5
3.5
4
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
3.5
4
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
14
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
935
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
-144
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
699
mV
1
Crossing Point Voltage
VXABS
Single-ended Measurement
300
438
550
mV
1,3,4
Crossing Point Variation VXABSVAR
Single-ended Measurement
60
140
mV
1,3,5
Duty Cycle
DCYC
Differential Measurement
45
50.4
55
%
1
CPU Jitter - Cycle to
Cycle
CPUJC2C
Differential Measurement
52
85
ps
1
SRC Jitter - Cycle to
Cycle
SRCJC2C
Differential Measurement
62
85
ps
1
DOT Jitter - Cycle to
Cycle
DOTJC2C
Differential Measurement
150
250
ps
1
SRC Skew
SRCSKEW
Differential Measurement, all SRC from
same PLL
93
200
ps
1
Electrical Characteristics - Phase Jitter
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNITS
NOTES
tjphPCIe1
PCIe Gen 1 REFCLK phase jitter
43
86
ps
1,2,3
tjphPCIe2Lo
PCIe Gen 2 REFCLK phase jitter
Lo-band content
1.8
3
ps
(RMS)
1,2,3
tjphPCIe2Hi
PCIe Gen 2 REFCLK phase jitter
Hi-band content
2.5
3.1
ps
(RMS)
1,2,3
Notes on Phase Jitter:
2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12
3 Applies to output pairs 10/11, 14/15, 18/19, and 23/24 when pins 21 and 31 are set to 1, and CPU is 100MHz.
Jitter, Phase
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
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