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參數(shù)資料
| 型號： | 9LRS4103BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-32 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 188K |
| 代理商： | 9LRS4103BKLFT |
IDT PC MAIN CLOCK
1520D—01/06/11
ICS9LRS4103
PC MAIN CLOCK
11
Byte 0 FS Readback and PLL Selection Register
Bit
Pin
Name
Description
Type
0
1
Default
7
FSLC
CPU Freq. Sel. Bit
R
Latch
6
Reserved
RW
-
0
5
Reserved
RW
-
1
4
iAMT_EN
Set via SMBus
RW
(Sticky 1)
Legacy Mode
iAMT Enabled
0
3
Reserved
RW
0
2
SEL_120M#
Selects pins #10/11 to be 120MHz or 100MHz
R
DISP (120MHz)
SRC (100MHz)
Latch
1
SEL_SATA_NS#
Select source for SATA clock
R
SATA
(100MHz_nonSS)
SRC1
(100MHz SS)
Latch
0PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.
RW
Configuration Not
Saved
Configuration
Saved
1
Byte 1 CPU/SRC Spread Selection Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
0
6
CK505 PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
5
Reserved
RW
-
0
4
Reserved
RW
-
0
3
Reserved
RW
-
0
2
Reserved
RW
-
0
1
Reserved
RW
-
0
Reserved
RW
-
1
Byte 2 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
REF_3L_OE
Output enable for REF0
RW
Output Disabled
Output Enabled
1
6
Reserved
RW
-
1
5
Reserved
RW
-
1
4
Reserved
RW
-
1
3
Reserved
RW
-
1
2
Reserved
RW
-
1
Reserved
RW
-
1
0
Reserved
RW
-
1
Byte 3 Reserved Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
1
6
Reserved
RW
-
1
5
Reserved
RW
-
1
4
Reserved
RW
-
1
3
Reserved
RW
-
1
2
Reserved
RW
-
1
Reserved
RW
1
0
Reserved
RW
-
1
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