參數(shù)資料
型號： 9LRS4103BKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC32
封裝： ROHS COMPLIANT, PLASTIC, MLF-32
文件頁數(shù)： 13/15頁
文件大?。?/td> 188K
代理商： 9LRS4103BKLFT
IDT PC MAIN CLOCK
1520D—01/06/11
ICS9LRS4103
PC MAIN CLOCK
7
CPU
SRC/SATA
DOT96
CK_SSC_DISP
100
ppm
85
250
125
ps
-0.50%
0
-0.50%
%
Clock Periods - Differential Outputs with Spread Spectrum Disabled
1 Clock
1us
0.1s
1us
1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
100.00
9.91400
9.99900
10.00000
10.00100
10.08600
ns
1,2
133.33
7.41425
7.49925
7.50000
7.50075
7.58575
ns
1,2
SATA
100.00
9.91400
9.99900
10.00000
10.00100
10.08600
ns
1,2
SRC
100.00
9.91400
9.99900
10.00000
10.00100
10.08600
ns
1,2
CK_SSC_DISP
120.00
8.20750
8.33250
8.33333
8.33417
8.45917
ns
1,2
DOT96
96.00
10.16563
10.41563
10.41667
10.41771
10.66771
ns
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock
1us
0.1s
1us
1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
99.75
9.91406
9.99906
10.02406
10.02506
10.02607
10.05107
10.13607
ns
1,2
133.00
7.41430
7.49930
7.51805
7.51880
7.51955
7.53830
7.62330
ns
1,2
SRC
99.75
9.91406
9.99906
10.02406
10.02506
10.02607
10.05107
10.13607
ns
1,2
CK_SSC_DISP
119.70
8.20755
8.33255
8.35338
8.35422
8.35505
8.37589
8.50089
ns
1,2
1Guaranteed by design and characterization, not 100% tested in production.
PPM tolerance
Cycle to Cycle Jitter
2 All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
Measurement Window
Units
SSC ON
Center
Freq.
MHz
Notes
CPU
Measurement Window
Units
Spread
SSC OFF
Center
Freq.
MHz
CPU
Notes
Differential Clock Tolerances
PD# Power Management
Device State
w/o Latched input w/Latched input
Latches Open
Power Down
M1
Virtual Power Cycle to
Latches Open
CK= Pull down, CK#
= Low
CPU0
CK= Pull down, CK#
= Low
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
Running
Single-ended Clocks
Differential Clocks
Low
Hi-Z
CK= Pull down, CK#
= Low
CK= Pull down, CK#
= Low
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參數(shù)描述
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