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| 型號： | 9S12H256BDGV1 |
| 英文描述： | 9S12H256B Device Guide |
| 中文描述： | 9S12H256B設(shè)備指南 |
| 文件頁數(shù)： | 100/130頁 |
| 文件大?。?/td> | 2171K |
| 代理商： | 9S12H256BDGV1 |
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MC9S12H256 Device User Guide — V01.18
100
operatingconditionsarelessthanworstcaseorleakage-inducederrorisacceptable,largervaluesofsource
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage
≤
1LSB, then the external filter capacitor, C
f
≥
1024 * (C
INS
– C
INN
).
A.2.2.3 Current Injection
There are two cases to consider.
1.
A current is injected into the channel being converted. The channel being stressed has conversion
valuesof$3FF($FFin8-bitmode)foranaloginputsgreaterthanV
RH
and$000forvalueslessthan
V
RL
unless the current is higher than specified as disruptive condition.
Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
ERR
= K * R
S
*
I
INJ
, with I
INJ
being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
2.
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
C Max input Source Resistance
R
S
–
–
1
K
2
T
Total Input Capacitance
Non Sampling
Sampling
C
INN
C
INS
10
22
pF
3
C Disruptive Analog Input Current
I
NA
–2.5
2.5
mA
4
C Coupling Ratio positive current injection
K
p
10
–4
A/A
5
C Coupling Ratio negative current injection
K
n
10
–2
A/A
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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