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| 型號(hào)： | 9S12H256BDGV1 |
| 英文描述： | 9S12H256B Device Guide |
| 中文描述： | 9S12H256B設(shè)備指南 |
| 文件頁(yè)數(shù)： | 72/130頁(yè) |
| 文件大小： | 2171K |
| 代理商： | 9S12H256BDGV1 |
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MC9S12H256 Device User Guide — V01.18
72
even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
4.2.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups
enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
ThepinsassociatedwithPortEbits6,5,3,and2cannotbeconfiguredfortheiralternatefunctionsIPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
Innormalsinglechipmode,theMODEregisteriswritableonetime.Thisallowsauserprogramtochange
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
PortE,bit4canbeconfiguredforafree-runningEclockoutputbyclearingNECLK=0.Typicallytheonly
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.1.2 Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
PortEbit4isconfiguredastheEclockoutputsignal.Thesesignalsallowexternalmemoryandperipheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
F
For More Information On This Product,
Go to: www.freescale.com
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