參數(shù)資料
型號： 9S12H256BDGV1
英文描述： 9S12H256B Device Guide
中文描述： 9S12H256B設(shè)備指南
文件頁數(shù)： 21/130頁
文件大小： 2171K
代理商： 9S12H256BDGV1
21
Figure 1-1 MC9S12H256 Block Diagram
EXTAL
XTAL
RESET
BKGD
XIRQ
IRQ
ECLK
MODA
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
Single-wire Background
Debug Module
PLL
PA4
PA5
PA3
PA2
PA1
PA0
PA7
PA6
TEST
PB4
PB5
PB0
PB1
PB7
PB6
FP4
FP5
FP3
FP2
FP1
FP0
FP7
FP6
PE4
PE5
PE6
PE0
PE1
IOC2
IOC3
IOC6
IOC7
IOC0
IOC4
IOC5
RXD0
TXD0
SDI/MISO
SDO/MOSI
PS3
PS4
PS5
PS6
PS7
PS0
PS2
SCI1
RXD1
TXD1
Pulse
Width
Modulator
(PWM)
PW2
PW3
PW4
PW5
PW0
PW1
PP3
PP4
PP5
PP0
PP1
PP2
PK3
PK7
PK0
PK1
PK2
SCK
SS
SPI
RXCAN0
TXCAN0
PM2
PM3
CAN1
RXCAN1
TXCAN1
PM4
PM5
Pin
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
KWH0
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
D
D
P
P
D
P
P
D
P
D
P
D
P
D
D
P
Interrupt
Logic
FP12
FP13
FP11
FP10
FP9
FP15
FP14
BP0
BP1
BP2
BP3
FP23
PL3
PL4
PL2
PL1
PL0
D
P
FP19
FP28
FP18
FP17
FP16
PE7
PE3
P
D
PE2
FP22
FP21
FP20
VLCD
VLCD
M0C0M
M0C0P
M0C1M
M0C1P
M1C0M
M1C0P
M1C1M
M1C1P
PU3
PU4
PU5
PU6
PU7
PU0
PU1
PU2
P
D
PWM0
PWM1
MOTOR0
PWM2
PWM3
MOTOR1
LCD
Driver
SCI0
CAN0
MODB
Integration
Module
VDXFC
VSSPLL
CPU12
Clock and
Reset
Generation
Module
P
D
PB3
PB2
PIX0
PIX1
PIX2
PIX3
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
P
D
FP24
FP25
FP26
FP27
M2C0M
M2C0P
M2C1M
M2C1P
M3C0M
M3C0P
M3C1M
M3C1P
PV3
PV4
PV5
PV6
PV7
PV0
PV1
PV2
P
D
PWM4
PWM5
MOTOR2
PWM6
PWM7
MOTOR3
M4C0M
M4C0P
M4C1M
M4C1P
M5C0M
M5C0P
M5C1M
M5C1P
PW3
PW4
PW5
PW6
PW7
PW0
PW1
PW2
P
D
PWM8
PWM9
MOTOR4
PWM10
PWM11
MOTOR5
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN00
AN01
PAD03
PAD04
PAD05
PAD06
PAD07
PAD08
PAD09
PAD10
PAD00
PAD01
PAD02
VRH
VRL
AN10
AN11
AN12
AN13
AN14
AN15
PAD11
PAD12
PAD13
PAD14
PAD15
VDDA
VSSA
Analog to
Digital
Converter
P
VRH
VRL
VDDA
VSSA
KWJ2
KWJ3
KWJ0
PJ3
PJ0
PJ1
PJ2
D
P
256k Bytes Flash EEPROM
4k Bytes EEPROM
12K Bytes RAM
M
P
DATA15
MOTOR0 and MOTOR1 Supply
VDDM1
VSSM1
MOTOR2 and MOTOR3 Supply
VDDM2
VSSM2
MOTOR4 and MOTOR5 Supply
VDDM3
VSSM3
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
Multiplexed
Wide
Bus
Multiplexed
Narrow
Bus
ECS/ROMONE
XADDR14
XADDR15
XADDR16
XADDR17
NOACC/XCLKS
LSTRB/TAGLO
R/W
VDDR
VDD1
VSS1,VSS2
Voltage Regulator
Input Capture and
Output Compare
Timer
SDA
SCL
PM0
PM1
IIC
VDDX1,2
VSSX1,2
VSSPLL
PLL 2.5V
I/O Driver 5V
A/D Converter 5V &
Voltage Regulator
Reference
VDDPLL
VDD1
VSS1,2
Internal Logic 2.5V
VDDA
VSSA
VDDR
VREG Input 5V
Supply pins
NOTE:
Not all
functionality shown
in this block
diagram is
available in all
packages!
PL7
PL6
FP31
FP30
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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