參數(shù)資料
型號： 9S12H256BDGV1
英文描述： 9S12H256B Device Guide
中文描述： 9S12H256B設(shè)備指南
文件頁數(shù)： 59/130頁
文件大?。?/td> 2171K
代理商： 9S12H256BDGV1
59
PM5
PM4
PM3
PM2
PM1
PM0
PP[5:2]
PP[1:0]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PT[7:4]
TXCAN1
RXCAN1
TXCAN0
RXCAN0
SCL
SDA
PWM[5:2]
PWM[1:0]
SS
SCK
MOSI
MISO
TXD1
RXD1
TXD0
RXD0
IOC[7:4]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX2
VDDX1
PERM/
PPSM
Disabled
Port M I/O, TX of CAN1
Port M I/O, RX of CAN1
Port M I/O, TX of CAN0
Port M I/O, RX of CAN0
Port M I/O, SCL of IIC
Port M I/O, SDA of IIC
Port P I/O, PWM channels
Port P I/O, PWM channels
Port S I/O, SS of SPI
Port S I/O, SCK of SPI
Port S I/O, MOSI of SPI
Port S I/O, MISO of SPI
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Port T I/O, Timer channels
Port T I/O, Timer channels, LCD
driver
PERP/
PPSP
Disabled
PERS/
PPSS
Disabled
PERT/
PPST
Down
PT[3:0]
IOC[3:0]
FP[27:24]
—
VDDX1
PU[3:0]
M0C0M
M0C0P
M0C1M
M0C1P
M1C0M
M1C0P
M1C1M
M1C1P
M2C0M
M2C0P
M2C1M
M2C1P
M3C0M
M3C0P
M3C1M
M3C1P
M4C0M
M4C0P
M4C1M
M4C1P
M5C0M
M5C0P,
M5C1M
M5C1P
—
—
VDDM
PERU/
PPSU
Disabled
Port U I/O, Motor0 of MC
PU[7:4]
—
—
VDDM
Port U I/O, Motor1 of MC
PV[3:0]
—
—
VDDM
PERV/
PPSV
Disabled
Port V I/O, Motor2 of MC
PV[7:4]
—
—
VDDM
Port V I/O, Motor3 of MC
PW[3:0]
—
—
VDDM
PERW/
PPSW
Disabled
Port W I/O, Motor4 of MC
PW[7:4]
—
—
VDDM
Port W I/O, Motor5 of MC
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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