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1.0
A28F200BR
5
ADVANCE INFORMATION
PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
automotive version of the 28F200BR family of boot
block flash memory devices.
This device continues to offer the same
functionality as earlier
“BX” devices but adds the
capability of performing program and erase
operations with a 5V or 12V V
PP
. The A28F200BR
automatically senses which voltage is applied to
the V
PP
pin and adjusts its operation accordingly.
1.1
New Features in the
SmartVoltage Products
The new SmartVoltage boot block flash memory
family offers identical operation as the current
BX/BL 12V program products, except for the
differences listed below. All other functions are
equivalent
to
current
signatures, write commands, and pinouts.
products,
including
WP# pin has replaced a DU pin. See Table 1
for details.
5V program/erase operation has been added
that
uses
proven
techniques with 5V ± 10% applied to V
PP.
program
and
erase
If you are designing with existing BX 12V V
boot
block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1.
Connect WP# (DU on existing products) to a
control signal, V
CC
or GND.
If adding a switch on V
PP
for write protection,
switch to GND for complete write protection.
Allow for connecting 5V to V
PP
instead of 12V,
if desired.
2.
3.
1.2
Main Features
Intel’s SmartVoltage technology provides the most
flexible
voltage
solution
SmartVoltage provides two discrete voltage supply
pins, V
CC
for read operation, and V
PP
for program
and erase operation. Discrete supply pins allow
system designers to use the optimal voltage levels
for their design. For program and erase
in
the
industry.
operations, 5V V
PP
operation eliminates the need
for in system voltage converters, while 12V V
PP
operation provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is already
available.
The 28F200 boot block flash memory family is a
very high-performance, 2-Mbit (2,097,152 bit) flash
memory family organized as either 256 Kwords
(131,072 words) of 16 bits each or 512 Kbytes
(262,144 bytes) of 8 bits each.
Separately erasable blocks, including a hardware-
lockable boot block (16,384 bytes), two parameter
blocks (8,192 Bytes each) and main blocks (one
block of 98,304 bytes and one block of 131,072
bytes) define the boot block flash family
architecture. See Figure 3 for memory maps. Each
parameter block can be independently erased and
programmed 10,000 times. Each main block can
be erased 1,000 times.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B suffix) of
the address map in order to accommodate
different microprocessor protocols for boot code
location. The hardware-lockable boot block
provides complete code security for the kernel
code required for system initialization. Locking and
unlocking of the boot block is controlled by WP#
and/or RP# (see Section 3.4 for details).
The Command User Interface (CUI) serves as the
interface
between
the
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write
State
Machine
executes the algorithms and timings necessary for
program
and
erase
verifications,
thereby
microprocessor or microcontroller of these tasks.
The Status Register (SR) indicates the status of
the WSM and whether it successfully completed
the desired program or erase operation.
microprocessor
or
(WSM)
automatically
operations,
unburdening
including
the
Program and erase automation allows program
and erase operations to be executed using an
industry-standard two-write command sequence to
the CUI. Data writes are performed in word or byte
increments. Each byte or word in the flash
memory can be programmed independently of
other memory locations, unlike erases, which
erase all locations within a block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power