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參數(shù)資料
| 型號： | A28F200BR-B |
| 廠商： | Intel Corp. |
| 英文描述： | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| 中文描述： | 2兆位（256K × 8）開機區(qū)塊快閃記憶體（2兆位（128K的× 16）引導塊閃速存儲器） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 440K |
| 代理商： | A28F200BR-B |
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E
A28F200BR
9
ADVANCE INFORMATION
Table 1. 28F200 Pin Descriptions
(Continued)
Symbol
Type
Name and Function
WP#
INPUT
WRITE PROTECT:
Provides a method for unlocking the boot block in a
system without a 12V supply.
When WP# is at logic low, the boot block is locked
, preventing
program and erase operations to the boot block. If a program or erase
operation is attempted on the boot block when WP# is low, the
corresponding status bit (bit 4 for program, bit 5 for erase) will be set in
the Status Register to indicate the operation failed.
When WP# is at logic high, the boot block is unlocked
and can be
programmed or erased.
NOTE:
This feature is overridden and the boot block unlocked when RP#
is at V
HH
. See Section 3.4 for details on write protection.
BYTE#
INPUT
BYTE# ENABLE:
Controls whether the device operates in the byte-wide
(x8) mode or the word (x16) mode. The BYTE# input must be controlled
at CMOS levels to meet the CMOS current specification in the standby
mode.
When BYTE# is at logic low, the byte-wide mode is enabled. A 19-bit
address is applied on A
-1
to
A
17
, and 8 bits of data is read and written on
DQ
0
-DQ
7
.
When BYTE# is at logic high, the word-wide mode is enable. An 18-bit
address is applied on A
0
to A
17
and 16 bits of data is read and written on
DQ
0
- DQ
15
.
V
CC
DEVICE POWER SUPPLY:
5.0V
±
10%
V
PP
PROGRAM/ERASE POWER SUPPLY:
For erasing memory array blocks
or programming data in each block, a voltage either of 5V
±
10% or 12V
±
5% must be applied to this pin. When V
PP
< V
PPLK
all blocks are locked
and protected against Program and Erase commands.
GND
GROUND:
For all internal circuitry.
NC
NO CONNECT:
Pin may be driven or left floating.
2.0
PRODUCT DESCRIPTON
2.1
Memory Blocking Organization
This product family features an asymmetrically-
blocked architecture enhancing system memory
integration.
Each
block
independently of the others up to 10,000 times. The
block sizes have been chosen to optimize their
functionality for common applications of nonvolatile
storage. For the address locations of the blocks,
see the memory maps in Figure 3.
can
be
erased
2.1.1
ONE 16-KB BOOT BLOCK
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
erasure. The protection of the boot block is
controlled using a combination of the V
PP
, RP#, and
WP# pins, as is detailed in Table 8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A28F200BR-T | 2-MBIT (128K x 16) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F200BX-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F400BR-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導塊閃速存儲器) |
| A28F400BR-T | 4-MBIT (256K x16) Boot Block Flash Memory(4兆位 (256K x16)引導塊閃速存儲器) |
| A28F400BX-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A28F200BR-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K X 16. 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BR-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BR-T/B |
| A28F200BR-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BX-B - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-T | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
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