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參數(shù)資料
| 型號： | A42MX16-3PL100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 107/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3PL100A |
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87
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
At the beginning of a telegram, the SSI Control loads the transmit buffer into the shift register
and proceeds immediately to shift data out. At the same time, incoming data is shifted into the
shift register. This incoming data is automatically loaded into the receive buffer when the com-
plete telegram has been received. In that way data can be simultaneously received and
transmitted.
The system is double buffered in the transmit direction and double buffered in the receive direc-
tion. When receiving data, however, a received character must be read from the SSI Data
Register (T2MDR) before the next character has been completely shifted in. Otherwise, the first
byte is lost.
Before data can be transferred, the SSI must first be activated. This is performed by means of
the SSI enable control bit (T2SSIE in the T2MRB register). There are two combinations of SCLK
polarity with respect to serial data, which are determined by control bit (T2CPOL in the T2MRB
register). The SSI has three status flags (T2RXF, T2TXF and T2TCF) in the status register
(T2IFR) and additional three interrupt mask bits (T2RXIM, T2TXIM and T2TCIM) in the interrupt
mask register (T2IMR). The status of the SSI buffer registers shown by the T2TXF bit for the
transmit buffer register (TXD) and the T2RXF bit for receive buffer register (RXD). The T2TCF
bit indicates the present status of the serial communication. Figure 3-35 shows an example of
transmit/receive operation from the SSI.
Figure 3-35. Example of Transmit/Receive Operation
For a serial data stream without a gap you must write T2MDR (TXD data) just after a
T2TXB-interrupt or after TXF-flag is set. For byte wise sending data you must write T2MDR
(TXD data) after a T2TXC-interrupt or after the T2TCF-flag is set.
LSB
MSB
LSB
MSB
3
0
1
2
54
76
3
0
1
2
54
76
3
0
1
2
54
76
LSB
MSB
Write T2MDR
(TXD data 3)
Write T2MDR
(TXD data 2)
Read T2MDR
(RXD data 1)
SCLK
(T2CPOL = 0)
SO/SI
T2SSIE
T2TXF
T2RXB
Interrupt
T2TXC
Interrupt
T2TXB
Interrupt
T2TCF
T2RXF
SCLK
(T2CPOL = 1)
Read T2MDR
(RXD data 2)
Read T2MDR
(RXD data 3)
Write T2MDR
(TXD data 1)
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL84 | 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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