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參數資料
| 型號： | A42MX16-3PL100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數： | 31/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3PL100A |
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18
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
3.5.7.1
Interrupt Response Time
The interrupt execution response for all the enabled Atmel AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt handling
routine is executed. During this four clock cycle periods, the Program Counter is pushed onto
the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is com-
pleted before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the
interrupt execution response time is increased by four clock cycles. This increase comes in addi-
tion to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
inr16, SREG; store SREG value
cli ; disable interrupts during timed sequence
sbiEECR, EEMWE; start EEPROM write
sbiEECR, EEWE
outSREG, r16; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
相關代理商/技術參數 |
參數描述 |
|---|---|
| A42MX16-3PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL84 | 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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