參數(shù)資料
型號(hào): A42MX36-CQ256A
元件分類(lèi): FPGA
英文描述: FPGA, 54000 GATES, CQFP256
封裝: CERAMIC, QFP-256
文件頁(yè)數(shù): 28/76頁(yè)
文件大?。?/td> 429K
代理商: A42MX36-CQ256A
MX Automotive Family FPGAs
1- 2 8
v2 .0
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
8.7
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
9.2
ns
tPWH
Minimum Pulse Width HIGH
FO = 16
FO = 128
4.2
4.4
ns
tPWL
Minimum Pulse Width LOW
FO = 16
FO = 128
4.2
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
0.7
1.0
ns
tP
Minimum Period
FO = 16
FO = 128
8.8
9.2
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
170
164
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
6.2
ns
tDHL
Data-to-Pad LOW
7.5
ns
tENZH
Enable Pad Z to HIGH
7.1
ns
tENZL
Enable Pad Z to LOW
8.8
ns
tENHZ
Enable Pad HIGH to Z
14.9
ns
tENLZ
Enable Pad LOW to Z
11
ns
dTLH
Delta LOW to HIGH
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
7.5
ns
tDHL
Data-to-Pad LOW
6.4
ns
tENZH
Enable Pad Z to HIGH
6.4
ns
tENZL
Enable Pad Z to LOW
9.2
ns
tENHZ
Enable Pad HIGH to Z
14.9
ns
tENLZ
Enable Pad LOW to Z
11
ns
dTLH
Delta LOW to HIGH
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
Table 1-6 A40MX04 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
4. Delays based on 35 pF loading.
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