參數(shù)資料
型號(hào)： A42MX36-CQ256A
元件分類： FPGA
英文描述： FPGA, 54000 GATES, CQFP256
封裝： CERAMIC, QFP-256
文件頁數(shù)： 29/76頁
文件大?。?/td> 429K
代理商： A42MX36-CQ256A
MX Automotive Family FPGAs
v2.0
1-29
Table 1-7 A42MX09 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
2.1
ns
tCO
Sequential Clock-to-Q
2.2
ns
tGO
Latch G-to-Q
2.1
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.5
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.2
ns
tRD2
FO=2 Routing Delay
1.7
ns
tRD3
FO=3 Routing Delay
2.0
ns
tRD4
FO=4 Routing Delay
2.4
ns
tRD8
FO=8 Routing Delay
4.0
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.6
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.8
ns
tA
Flip-Flop Clock Input Period
6.0
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.5
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
229
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.9
ns
tINYL
Pad-to-Y LOW
1.4
ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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