參數(shù)資料
型號: A42MX36-CQ256A
元件分類: FPGA
英文描述: FPGA, 54000 GATES, CQFP256
封裝: CERAMIC, QFP-256
文件頁數(shù): 42/76頁
文件大?。?/td> 429K
代理商: A42MX36-CQ256A
MX Automotive Family FPGAs
v2.0
1-41
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O
8.4
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O
11.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.10
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.10
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
6.1
ns
tDHL
Data-to-Pad LOW
4.2
ns
tENZH
Enable Pad Z to HIGH
4.6
ns
tENZL
Enable Pad Z to LOW
5.1
ns
tENHZ
Enable Pad HIGH to Z
9.2
ns
tENLZ
Enable Pad LOW to Z
8.6
ns
tGLH
G-to-Pad HIGH
8.8
ns
tGHL
G-to-Pad LOW
8.8
ns
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O
9.9
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O
13.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.12
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.12
ns/pF
Table 1-10 A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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