參數(shù)資料
型號(hào)： A42MX36-CQ256A
元件分類(lèi)： FPGA
英文描述： FPGA, 54000 GATES, CQFP256
封裝： CERAMIC, QFP-256
文件頁(yè)數(shù)： 76/76頁(yè)
文件大?。?/td> 429K
代理商： A42MX36-CQ256A
MX Automotive Family FPGAs
v2.0
1-3
D-modules, available in A42MX24 and A42MX36 devices,
contain wide-decode circuitry which provide a fast, wide-
input AND function similar to that found in CPLD
architectures (Figure 1-4). These modules are arranged
around the periphery of the device. The D-module allows
42MX devices to perform wide-decode functions at
speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH
or LOW assertion. The D-module output is hard-wired to
an output pin, but it can also be fed back into the array
to be incorporated into other logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules
that
have
been
optimized
for
synchronous
or
asynchronous applications. The SRAM modules are
arranged in 256-bit blocks that can be configured as 32x8
or 64x4. SRAM modules can be cascaded together to
form memory spaces of user-definable width and depth.
A block diagram of the 42MX dual-port SRAM block is
shown in Figure 1-5.
The 42MX SRAM modules are true dual-port structures
containing independent read and write ports. Each
SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]), and eight outputs (RD[7:0]) which are
connected to segmented vertical routing tracks.
The 42MX dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
fast FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory
functions, such as FIFOs, LIFOs, and RAM arrays. In
addition, unused SRAM blocks can be used to implement
registers for other logic within the design.
Figure 1-4 D-Module Implementation in 42MX Devices
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable
Inverter
Figure 1-5 42MX Dual-Port SRAM Block
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7:0]
Routing Tracks
[5:0]
RDAD[5:0]
REN
RCLK
Latches
WD[7:0]
WRAD[5:0]
Write
Logic
MODE
BLKEN
WEN
WCLK
[5:0]
Latches
Read
Logic
[7:0]
Latches
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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A42MX36-FBGG272 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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