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參數資料
| 型號： | A54SX32A-CQG208C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208 |
| 封裝： | CERAMIC, QFP-208 |
| 文件頁數： | 12/40頁 |
| 文件大小： | 738K |
| 代理商： | A54SX32A-CQG208C |
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2
Ge ne ra l Des c r i pt i o n
Actel’s SX-A family of FPGAs features a sea-of-modules
architecture
that
delivers
device
performance
and
integration levels not currently achieved by any other FPGA
architecture. SX-A devices greatly simplify design time,
enable dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient mapping
of synthesized logic functions. The routing and interconnect
resources are in the metal layers above the logic modules,
providing optimal use of silicon. This enables the entire
floor of the device to be spanned with an uninterrupted grid
of
fine-grained,
synthesis-friendly
logic
modules
(or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX-A devices employ both local and
general routing resources. The high-speed local routing
resources (DirectConnect and FastConnect) enable very
fast local signal propagation that is optimal for fast
counters, state machines, and datapath logic. The general
system of segmented routing tracks allows any logic module
in the array to be connected to any other logic or I/O
module. Within this system, propagation delay is minimized
by limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX-A devices gives fast and predictable
performance, allows 100 percent pin locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX-A’s flexible routing structure is a
hardwired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
setup times. SX-A devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
Q M L C e rtif i ca tio n
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense
for
monolithic
integrated
circuits.
QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military, and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
De vel o pm e n t Too l Su ppo r t
The SX-A devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place-and-route tools.
Designer Advantage, Actel’s suite of FPGA development
point tools for PCs and Workstations, includes the ACTgen
Macro Builder, Designer with DirectTime timing-driven
place-and-route and analysis tools, and device programming
software.
In addition, the SX-A devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100-percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an easy to
use integrated verification and logic analysis tool that can
sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
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相關代理商/技術參數 |
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| A54SX32A-FBG329 | 功能描述:IC FPGA SX 48K GATES 329-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX32A-FBGG329 | 功能描述:IC FPGA SX 48K GATES 329-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
| A54SX32A-FFG144 | 功能描述:IC FPGA SX 48K GATES 144-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:SX-A 標準包裝:90 系列:ProASIC3 LAB/CLB數:- 邏輯元件/單元數:- RAM 位總計:36864 輸入/輸出數:157 門數:250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
| A54SX32A-FFG256 | 功能描述:IC FPGA SX 48K GATES 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:SX-A 標準包裝:90 系列:ProASIC3 LAB/CLB數:- 邏輯元件/單元數:- RAM 位總計:36864 輸入/輸出數:157 門數:250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
| A54SX32A-FFG484 | 功能描述:IC FPGA SX 48K GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:SX-A 標準包裝:40 系列:SX-A LAB/CLB數:6036 邏輯元件/單元數:- RAM 位總計:- 輸入/輸出數:360 門數:108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
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