參數(shù)資料
型號: A54SX32A-CQG208C
元件分類: FPGA
英文描述: FPGA, 2880 CLBS, 32000 GATES, 206 MHz, CQFP208
封裝: CERAMIC, QFP-208
文件頁數(shù): 19/40頁
文件大?。?/td> 738K
代理商: A54SX32A-CQG208C
26
A5 4S X72 A Ti mi n g Ch ar ac t e r i s t i c s
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CCA = 2.3 V, VCCI = 3.0 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
1.3
1.5
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.2
ns
tRD1
FO=1 Routing Delay
0.5
0.6
ns
tRD2
FO=2 Routing Delay
0.7
0.8
ns
tRD3
FO=3 Routing Delay
0.9
1.0
ns
tRD4
FO=4 Routing Delay
1.2
1.3
ns
tRD8
FO=8 Routing Delay
2.0
2.4
ns
tRD12
FO=12 Routing Delay
2.9
3.5
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
1.1
1.4
ns
tCLR
Asynchronous Clear-to-Q
0.9
1.0
ns
tPRESET
Asynchronous Preset-to-Q
1.0
1.3
ns
tSUD
Flip-Flop Data Input Setup
0.7
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
1.6
1.9
ns
tRECASYN
Asynchronous Recovery
0.4
0.5
ns
tHASYN
Asynchronous Hold Time
0.4
0.5
ns
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
0.9
1.0
ns
tINYL
Input Data Pad-to-Y LOW
1.4
1.6
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
0.5
0.6
ns
tIRD2
FO=2 Routing Delay
0.7
0.8
ns
tIRD3
FO=3 Routing Delay
0.9
1.0
ns
tIRD4
FO=4 Routing Delay
1.2
1.3
ns
tIRD8
FO=8 Routing Delay
2.0
2.4
ns
tIRD12
FO=12 Routing Delay
2.9
3.5
ns
Notes:
1.
For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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