參數(shù)資料
型號: ACE9030
廠商: Mitel Networks Corporation
英文描述: Radio Interface and Twin Synthesiser
中文描述: 無線接口和雙合成器
文件頁數(shù): 13/39頁
文件大?。?/td> 379K
代理商: ACE9030
ACE9030
13
Radio Interface Bus - Transmit
The output Preamble word begins with a fixed pattern
1 0 1 0 and then includes the source code number (Y1, Y0) for
the Result words and the status of the Lock Detect from the
synthesiser, all as described in the section Polling A to D
Converter.
The ACE9030 only drives the bus in response to a request
for data by a Normal command as described above. To avoid
any bus contention, there is a delay from the end of a data
request to the start of the response, see figure 10. The data will
start on the fifth rising edge of CL after the rising edge of
LATCHB.
Fig.10 Radio Interface transmit bus timing
Synthesiser Bus - Receive Only
The overall format to control the synthesiser is basically the
same as for the Radio Interface. There is an option of a 32 bit
sequence for the A word. The width of the LATCHC pulse is
used to set the duration of speed-up mode when changing
channels.
Fig.11 Synthesiser bus timing
CL
DATA3
LATCHB
PREAMBLE
RESULT1
RESULT2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 2 3 4 5
CL
DATA (WORD A)
DATA (WORD B)
DATA (WORD C)
DATA (WORD D)
DATA (WORD A2)
LATCHC
DURATION OF MAIN SYNTHESISER SPEED-UP MODE
DATA (DUMMY WORD)
- ONLY USED TO ALLOW
LATCHC TO REMAIN HIGH
LG
DA
DM
SA
SM
NR
0 1 0 1
1
1
1
1
FMOD
N1
N2
CN
NF
0 0 0 1
1 0 0 1
D
DM
N1
N2
NF
0
0 0
K
L
CN
7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0
1 0 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0
11 10 9 8 7 6 5 4 3 2 1 0
not used
1 0 1 0 11 10 9 8 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0
not used - any data may fill space
TEST
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