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參數(shù)資料
| 型號： | ACE9030 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Radio Interface and Twin Synthesiser |
| 中文描述： | 無線接口和雙合成器 |
| 文件頁數(shù)： | 34/39頁 |
| 文件大小： | 379K |
| 代理商： | ACE9030 |
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34
ACE9030
APPLICATIONS HINTS
V
DD
& V
SS
Supply Pins
All V
pins must be well decoupled to ground. All V
pins
must be connected through very low impedance lines to the
ground point.
Serial Bus
Edge speeds on the serial bus should not be too fast in
order to avoid ringing which then can cause significant modu-
lation of the synthesisers, including CLK8.
Loop Filters
Both synthesisers use passive loop filters and typical
circuits can be either of these two configurations; the need for
the extra roll-off in the right hand circuit is only for the more
critical applications.
The loop filter needed is partly set by the application
specification and partly by the architectural design of the
cellphone. The main synthesiser will need to hop channels at
a rate set by the hand-off times of the network and so is well
defined. The auxiliary synthesiser is always on the same
Fig. 29 Typical Synthesiser Loop Filters
frequency and so could be a very slow loop to lock but in many
systems it will be powered down for as much time as possible
to economise on battery use and will then need to power-up
and lock quickly, leading to a more complex filter.
The values of the components in these filters may be
calculated with the help of appendix AB43 in the Personal
Communications Handbook or for a more complete analysis
the application note AN94, available from Mitel Semiconduc-
tor Marketing Department, may be used. This note was written
specifically for the NJ88C33 synthesiser but the mathematics
apply equally well to the ACE9030.
AFC Circuit
Fig. 30 Simplified Receiver Architecture
In order to fine trim the crystal oscillator frequency to the
correct value the ACE9030 includes a sampling circuit to
convert the final intermediate frequency signal (input on
AFCIN) to a logic signal and then to mix it down to a low
frequency output (on AFCOUT) for counting in the
microcontroller. The operation of this system can be explained
with the use of a simplified block diagram of the receiver
architecture as in figure 30.
Most receivers run the first mixer with a high-side local
oscillator controlled by the Main synthesiser, so a positive
crystal frequency error will give an increased First I.F. This is
then mixed down further by a low-side second oscillator, LO2
in the ACE9030, derived by multiplying the same crystal as
used for the Main synthesiser. A positive crystal frequency
error would now give a reduced second I.F. if the error in the
first I.F. is ignored, but the overall effect is an increase by an
amount slightly smaller than the increase in the first I.F.
The second I.F. signal AFCIN at around 450 kHz drives
the F.M. Discriminator to recover the modulation and also
feeds a third mixer where high-side injection is used to give a
very low output frequency, around 54 kHz, and is output on
AFCOUT for counting. This third mixer is driven by a clock
derived from the crystal but at a much reduced frequency so
the effect of the high-side mixing dominates to give an output
which drops in frequency when the crystal has a positive
frequency error. As a result of the chain of mixing stages the
error in the first local oscillator due to the crystal frequency will
give a similar frequency shift at the output of the third mixer
which is then a large percentage change in the frequency of
AFCOUT so it is possible to measure AFCOUT against the
crystal to determine the trim needed.
To illustrate the sensitivity of the AFC loop a numerical
example can be used, and in the calculations that follow the
selection of parameters for the synthesisers are also included
to show how some choices are made.
Assume the required receiver frequency is AMPS chan-
nel 1, that is 870·030 MHz and that the cellular terminal is built
with a 45 MHz first I.F., a 450 kHz second I.F., and a
14·85 MHz crystal.
To receive 870·030 MHz with a 45 MHz first I.F. needs
the first local oscillator, the Main synthesiser, to run at a
frequency of 870·030 + 45·000 = 915·030 MHz when using
high-side injection. For AMPS the most convenient compari-
son frequency is the channel spacing of 30 kHz so the total
division from VCO to phase comparator (N
as used else-
where) will be 30501 for this channel and the reference
PDA
VCO
OR
PDP
PDI
VCO
FIRST
I.F
SECOND
I.F
LO2
MAIN
SYNTH
RX BAND
RECEIVED
SIGNAL FROM
BASESTATION
AFCIN
AFCOUT
AFC SAMPLE
AT 504 kHz
ACE9030
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACE9040 | Audio Processor Advance Information |
| ACE9050 | System Controller and Data Modem(為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器) |
| ACE9050 | System Controller and Data Modem Advance Information |
| ACFA-450 | AM CERAMIC FILTERS |
| ACFA-455 | AM CERAMIC FILTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACE9030IGFP1N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP1R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP2N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP2R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030M | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Radio Interface and Twin Synthesiser |
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