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參數(shù)資料
| 型號(hào)： | ACE9030 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Radio Interface and Twin Synthesiser |
| 中文描述： | 無線接口和雙合成器 |
| 文件頁數(shù)： | 9/39頁 |
| 文件大小： | 379K |
| 代理商： | ACE9030 |
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ACE9030
9
ELECTRICAL CHARACTERISTICS
These characteristics apply over these ranges of conditions (unless otherwise stated):
T
AMB
= – 40
°
C to + 85
°
C, all V
DD
= + 3·6 to + 5·0 V, GND ref. = V
SS
A.C. Characteristics (continued)
Parameter
LO2 Multiplier
Amplitude
Reference frequency content of output
2nd, 4th harmonic content of output
5th harmonic of output
6th and higher harmonics in output
SYNTHESISERS
Reference divider
Reference divider input frequency
Drive level into CIN1 from external oscillator
Note
8. To simplify single ended drive there is a resistor between FIA and FIAB and another between FIM and FIMB. In this mode the inputs should
drive FIA or FIM with D.C. coupling and the other inputs FIAB and FIMB should be decoupled to ground by external capacitors.
Min.
Typ.
Max.
Unit
Conditions
235
500
-10.5
-13.5
-15
-20
mV
rms
Circuit as in fig. 15,
dBc
dBc
dBc
dBc
5
30
MHz
mV
pk-pk
With crystal oscillator
powered down
pF
k
400
CIN1 input capacitance
CIN1 input resistance
Auxiliary synthesiser
FIA input frequency
Rise and fall times of inputs
Timing Skew between FIA and FIAB
10
10
10
135
10
±
2
MHz
ns
ns
signal Both maxima
period must be met
mV
pk-pk
Each input, 5 to 50 &
99 to 135 MHz
mV
pk-pk
Each input,
50 to 99 MHz
mV
pk-pk
One input, 5 to 50 &
99 to 135 MHz
mV
pk-pk
One input,
50 to 99 MHz
V
V
DD
= 3.6V
V
V
DD
= 5V
pF
k
Note 8
MHz
May be a sinewave
See Fig. 6
or
±
10%
FIA, FIAB differential signal level with both
sides driven
180
100
FIA single input drive level with FIAB
decoupled to V
SS
360
200
FIA, FIAB common mode range
FIA, FIAB common mode range
FIA, FIAB input capacitance
FIA, FIAB differential input resistance
Auxiliary Synthesiser comparison frequency
Main Synthesiser
FIM input frequency
Rise and fall times of inputs
FIM - FIMB Timing Skew
V
DD
– 1·7
2.8
V
DD
– 0·7
V
DD
– 0·85
10
10
2
4
20
50
±
2
MHz
ns
ns
signal Both maxima
period must be met
mV
pk-pk
Each input,
4 to 20 MHz
mV
pk-pk
One input,
4 to 20 MHz
V
V
DD
=3.6V
V
V
DD
=5V
pF
k
Note 8
ns
MHz
See Fig. 6
or
±
10%
FIM, FIMB differential signal level
with both sides driven.
FIM single input drive level
with FIMB decoupled to V
SS
FIM, FIMB common mode range
FIM, FIMB common mode range
FIM, FIMB input capacitance
FIM, FIMB differential input resistance
Delay FIM rising to MODMP/MODMN changing
Main Synthesiser comparison frequency
100
200
1000
V
DD
– 1·7
2·8
V
DD
– 0·7
V
DD
– 0·85
10
10
30
2
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|---|---|
| ACE9040 | Audio Processor Advance Information |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACE9030IGFP1N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP1R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP2N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030IGFP2R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer |
| ACE9030M | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Radio Interface and Twin Synthesiser |
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