參數(shù)資料
型號(hào)： AD5305ARMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT 2WIRE I2C 10-MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 6µs
位數(shù)： 8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 5mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 167k
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
AD5305/AD5315/AD5325
Rev. G | Page 4 of 24
A Version1
B Version1
Parameter2
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
LOGIC INPUTS (A0
Input Current
±1
μA
Input Low Voltage, VIL
0.8
V
VDD = 5 V ± 10%
0.6
V
VDD = 3 V ± 10%
0.5
V
VDD = 2.5 V
Input High Voltage, VIH
2.4
V
VDD = 5 V ± 10%
2.1
V
VDD = 3 V ± 10%
2.0
V
VDD = 2.5 V
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)5
Input High Voltage, VIH
0.7
VDD
VDD +
0.3
0.7
VDD
VDD +
0.3
V
SMBus compatible at VDD < 3.6 V
Input Low Voltage, VIL
0.3
0.3 VDD
0.3
0.3 VDD
V
SMBus compatible at VDD < 3.6 V
Input Leakage Current, IIN
±1
μA
Input Hysteresis, VHYST
0.05
VDD
0.05
VDD
V
Input Capacitance, CIN
8
pF
Glitch Rejection
50
ns
Input filtering suppresses noise spikes
of less than 50 ns
LOGIC OUTPUT (SDA)5
Output Low Voltage, VOL
0.4
V
ISINK = 3 mA
0.6
V
ISINK = 6 mA
Three-State Leakage Current
±1
μA
Three-State Output
Capacitance
8
pF
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD (Normal Mode)7
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
600
900
600
900
μA
VDD = 2.5 V to 3.6 V
500
700
500
700
μA
IDD (Power-Down Mode)
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
0.2
1
0.2
1
μA
IDD = 4 μA (maximum) during
0 readback on SDA
VDD = 2.5 V to 3.6 V
0.08
1
0.08
1
μA
IDD = 1.5 μA (maximum) during
0 readback on SDA
1 Temperature range (A, B version): 40°C to +105°C; typical at +25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5 Guaranteed by design and characterization, not production tested.
6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be
positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
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