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參數(shù)資料
| 型號： | AD5305ARMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 2WIRE I2C 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5305/AD5315/AD5325
Rev. G | Page 5 of 24
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Version1
Parameter2, 3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
VREF = VDD = 5 V
AD5305
6
8
μs
scale to scale change (0×40 to 0×C0)
AD5315
7
9
μs
scale to scale change (0×100 to 0×300)
AD5325
8
10
μs
scale to scale change (0×400 to 0×C00)
Slew Rate
0.7
V/μs
Major-Code Transition Glitch Energy
12
nV-s
1 LSB change around major carry
Digital Feedthrough
1
nV-s
Digital Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion
70
dB
VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Temperature range (A, B version): 40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization, not production tested.
3 See the Terminology section.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Limit at TMIN, TMAX (A, B Version)
Unit
Conditions/Comments
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD,STA, start/repeated start condition hold time
t5
100
ns min
tSU,DAT, data setup time
t63
0.9
μs max
tHD,DAT, data hold time
0
μs min
tHD,DAT, data hold time
t7
0.6
μs min
tSU,STA, setup time for repeated start
t8
0.6
μs min
tSU,STO, stop condition setup time
t9
1.3
μs min
tBUF, bus-free time between a stop and a start condition
t10
300
ns max
tR, rise time of SCL and SDA when receiving
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
250
ns max
tF, fall time of SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
300
ns max
tF, fall time of SCL and SDA when receiving
20 + 0.1 CB4
ns min
tF, fall time of SCL and SDA when transmitting
CB4
400
pF max
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
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