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參數(shù)資料
| 型號(hào)： | AD5532ABCZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
AD5532
Rev. D | Page 10 of 20
Table 7. Pin Function Descriptions
Pin
Function
AGND (1–2)
Analog GND pins.
AVCC (1–2)
Analog Supply pins. Voltage range from 4.75 V to 5.25 V.
VDD (1–4)
VDD Supply pins. Voltage range from 8 V to 16.5 V.
VSS (1–4)
VSS Supply pins. Voltage range from –4.75 V to –16.5 V.
DGND
Digital GND pins.
DVCC
Digital Supply pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND (1–2)
Reference GND supply for all DACs.
REF_IN
Reference voltage for Channels 0–31.
REF_OUT
Reference Output Voltage.
VOUT (0–31)
Analog Output Voltages from the 32 channels.
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
A4–A1, A0
Parallel Interface: 5 address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Internal pull-up devices on these
logic inputs. Therefore, they can be left floating and default to a logic high condition.
CAL
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
CS/SYNC
This is the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface.
WR
Parallel interface: Write pin; active low. This is used in conjunction with the CS pin to address the device using the parallel
interface. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low
condition.
OFFSET_SEL
Parallel interface: Offset Select pin; active high. This is used to select the offset channel. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition
SCLK
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
DIN
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Internal pull-up devices on these logic
inputs. Therefore, they can be left floating and default to a logic high condition.
DOUT
Output from the DAC registers for read back. Data is clocked out on the rising edge of SCLK and is valid on the falling
edge of SCLK.
SER/PAR
This pin allows the user to select whether the serial or parallel interface is used. If the pin is tied low, the parallel interface
is used. If it is tied high, the serial interface is used. Internal pull-down devices on these logic inputs. Therefore, they can
be left floating and default to a logic low condition.
OFFS_IN
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the
user wants to drive this pin with the offset channel.
OFFS_OUT
Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span.
BUSY
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when
the acquisition operation is complete.
TRACK/RESET
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset
stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK
Input section for further information. This input can also be used as a means of resetting the complete device to its
power-on-reset conditions. This is achieved by applying a low-going pulse of between 90 ns and 200 ns to this pin. See
section on RESET Function for further details. Internal pull-up devices on these logic inputs. Therefore, they can be left
floating and default to a logic high condition.
00939-C-008
VOUT
IDEAL
TRANSFER
FUNCTION
UPPER
DEAD BAND
LOWER
DEAD BAND
OFFSET
ERROR
ACTUAL
TRANSFER
FUNCTION
GAIN ERROR +
OFFSET ERROR
VIN
2.96 3V
70mV
0V
00939-C-007
DAC CODE
0
16k
OUTPUT
VOLTAGE
IDEAL TRANSFER
FUNCTION
IDEAL GAIN
× REFIN
IDEAL GAIN
× 50mV
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
Figure 8. DAC Transfer Function (OFFS_IN=0)
Figure 9. ISHA Transfer Function
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| AD5532ABCZ-3 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5532ABCZ-5 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD5532B: 32-Channel. 14-Bit DAC with Precision Infinite Sample-and-Hold Mode (Rev A. 9/02) |
| AD5532BBC-1 | 制造商:Analog Devices 功能描述:DAC 32-CH 14-bit 74-Pin CSP-BGA Tray 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, 14-BIT DAC & SHA I.C. - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD5532BBCZ-1 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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